參數(shù)資料
型號: MAX117CPI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: +3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1UA Power-Down
中文描述: 8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 7/12頁
文件大小: 106K
代理商: MAX117CPI
M
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1μA Power-Down
_______________________________________________________________________________________
7
_______________Detailed Desc ription
Converter Operation
The MAX113/MAX117 use a half-flash conversion tech-
nique (see Functional Diagram in which two 4-bit flash
ADC sections achieve an 8-bit result. Using 15 com-
parators, the flash ADC compares the unknown input
voltage to the reference ladder and provides the upper
four data bits. An internal digital-to-analog converter
(DAC) uses the four most significant bits (MSBs) to
generate both the analog result from the first flash con-
version and a residue voltage that is the difference
between the unknown input and the DAC voltage. The
residue is then compared again with the flash com-
parators to obtain the lower four data bits (LSBs).
An internal analog multiplexer enables the devices to
read four (MAX113) or eight (MAX117) different analog
voltages under microprocessor (μP) control. One of the
MAX117’s analog channels, IN8, is internally hard-
wired and always reads V
REF+
when selected.
Power-Down Mode
In burst-mode or low-sample-rate applications, the
MAX113/MAX117 can be shut down between conver-
sions, reducing supply current to microamp levels (see
Typical Operating Characteristics). A logic low on the
PWRDN
pin shuts the devices down, reducing supply
current typically to 1μA when powered from a single
+3V supply. A logic high on
PWRDN
wakes up the
MAX113/MAX117, and the selected analog input enters
the track mode. The signal is fully acquired after 900ns
(this includes both the power-up delay and the
track/hold acquisition time), and a new conversion can
be started. If the power-down feature is not required,
connect
PWRDN
to V
DD
. For minimum current con-
sumption, keep digital inputs at the supply rails in
power-down mode. Refer to the Reference section for
information on reducing the reference current during
power-down.
___________________Digital Interfac e
The MAX113/MAX117 have two basic interface modes,
which are set by the MODE pin. When MODE is low,
the converters are in read mode; when MODE is high,
the converters are set up for write-read mode. The A0,
A1, and A2 inputs control channel selection, as shown
in Table 1. The address must be valid for a minimum
time, t
ACQ
, before the next conversion starts.
DATA
OUTPUTS
DATA
OUTPUTS
C
L
R
L
= 3k
C
L
a)
HIGH-Z TOVOH
b)
HIGH-Z TOVOL
R
L
= 3k
V
DD
Figure 1. Load Circuits for Data-Access Time Test
DATA
OUTPUTS
10pF
3k
10pF
a)
VOH TOHIGH-Z
b)
VOL TOHIGH-Z
3k
V
DD
DATA
OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
Table 1. Truth Table for Input Channel
Selection
MAX113
A1
0
0
1
0
1
0
IN1
IN2
IN3
IN4
IN5
1
1
IN6
IN7
IN8
(reads V
REF+
if selected)
0
0
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
1
MAX117
A1
0
0
0
SELECTED CHANNEL
A2
A0
A0
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MAX117EAI+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 4Ch 400ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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