參數(shù)資料
型號: MAX11635EEE+T
廠商: Maxim Integrated Products
文件頁數(shù): 13/24頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SRL 300KSPS 16QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
位數(shù): 12
采樣率(每秒): 300k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-QSOP
包裝: 標準包裝
輸入數(shù)目和類型: 4 單端,單極;2 差分,單極;2 差分,雙極
其它名稱: MAX11635EEE+TDKR
MAX11634–MAX11637
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
20
______________________________________________________________________________________
Internally Timed Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This is
the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX11634–MAX11637 then power up, scan all
requested channels, store the results in the FIFO, and
shut down. After the scan is complete, EOC is pulled
low and the results are available in the FIFO. EOC stays
low until CS is pulled low again.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eighth and ninth cycles, the pulse
width must be less than 100s. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
CS
DOUT
SCLK
CNVST
EOC
(CONVERSION2)
MSB1
LSB1
MSB2
(ACQUISITION1)
(ACQUISITION2)
(CONVERSION1)
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION.
Figure 5. Clock Mode 01
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
MSB1
LSB1
MSB2
(CONVERSION BYTE)
CS
DOUT
SCLK
DIN
EOC
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED.
Figure 6. Clock Mode 10
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MAX11636 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:12-Bit, 300ksps ADCs with Differential
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