參數(shù)資料
型號: MAX1162CCUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/18頁
文件大小: 0K
描述: IC ADC 16BIT 200KSPS 10UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 200k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 444mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個單端,單極
MAX1162
16-Bit, +5V, 200ksps ADC with 10A
Shutdown
10
______________________________________________________________________________________
Digital Interface
Initialization after Power-Up and
Starting a Conversion
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic high on CS places
the MAX1162 in shutdown (AutoShutdown) and places
DOUT in a high-impedance state. A logic low on CS
places the MAX1162 in the fully powered mode.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figures 6
and 7). Ensure that the duty cycle on SCLK is between
40% and 60% at 4.8MHz (the maximum clock frequen-
cy). For lower clock frequencies, ensure that the mini-
mum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz can
result in reduced accuracy due to leakage.
Note: Coupling between SCLK and the analog
inputs (AIN and REF) may result in an offset.
Variations in frequency, duty cycle, or other aspects
of the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence.
The analog input is stored in the capacitive DAC,
DOUT changes from high impedance to logic low, and
the ADC begins to convert after the sixth clock cycle.
SCLK drives the conversion process and shifts out the
conversion result on DOUT.
SCLK begins shifting out the data (MSB first) after the
falling edge of the 8th SCLK pulse. Twenty-four falling
clock edges are needed to shift out the eight leading
zeros and 16 data bits. Extra clock pulses occurring
after the conversion result has been clocked out, and
prior to the rising edge of CS, produce trailing zeros at
DOUT and have no effect on the converter operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX1162 in
shutdown. For maximum throughput, force CS low
again to initiate the next conversion immediately after
the specified minimum time (tCSW).
Note: Forcing
CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX1162 in shutdown.
CDAC 32pF
RIN
800
HOLD
CSWITCH
3pF
AIN
REF
GND
ZERO
CAPACITIVE DAC
AUTO-ZERO
RAIL
TRACK
Figure 5. Equivalent Input Circuit
CS
SCLK
20
16
24
12
14
8
6
DOUT
D15
D14
D13
D12
D11
D10
D9
D1
D0
D8
D5
D4
D3
D2
D7
D6
tCSH
tTR
tDO
tACQ
tCSS
tCH
tCL
tDV
Figure 6. External Timing Diagram
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MAX1162CE_B 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit, +5V, 200ksps ADC with 10レA Shutdown
MAX1162CEUB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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MAX1162CEUB+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 200ksps 4.096V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1162CEUB-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32