with Internal Temperature Sensor and VDD
參數(shù)資料
型號(hào): MAX1154BEUE+
廠商: Maxim Integrated Products
文件頁數(shù): 3/30頁
文件大?。?/td> 0K
描述: IC ADC 10BIT SYS MON 16TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
位數(shù): 10
采樣率(每秒): 94k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 15mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)單端,單極;4 個(gè)差分,單極;4 個(gè)差分,雙極
產(chǎn)品目錄頁面: 1395 (CN2011-ZH PDF)
MAX1153/MAX1154
Stand-Alone, 10-Channel, 10-Bit System Monitors
with Internal Temperature Sensor and VDD Monitor
______________________________________________________________________________________
11
During the acquisition interval, IN+ and IN- charge both
a positive (CHOLDP) and a negative (CHOLDN) sam-
pling capacitor. After completing the acquisition inter-
val, the T/H switches open, storing an accurate sample
of the differential voltage between IN+ and IN-. This
charge is then transferred to the ADC and converted.
Finally, the conversion result is transferred to the cur-
rent data register.
Temperature conversions require 46s (typ) and mea-
sure the difference between two sequential voltage
measurements (see the
Temperature Measurement
section for a detailed description).
Fully Differential Track/Hold (T/H)
The T/H acquisition interval begins with the rising edge
of CS (for manually triggered conversions) and is inter-
nally timed to 1.5s (typ). The accuracy of the input sig-
nal sample is a function of the input signal’s source
impedance and the T/H’s capacitance. In order to
achieve adequate settling of the T/H, limit the signal
source impedance to a maximum of 1k
Ω.
Input Bandwidth
The ADC’s input tracking circuitry has a 1MHz small-
signal bandwidth. To avoid high-frequency signals
aliasing into the frequency band of interest, anti-alias
prefiltering of the input signals is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
inputs to VDD and GND, allow the channel input pins to
swing from (VGND - 0.3V) to (VDD + 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDD by more than 50mV or
be lower than VGND by 50mV. If the analog input range
must exceed 50mV beyond the supplies, limit the input
current.
Single Ended/Differential
The MAX1153/MAX1154 use a fully differential ADC for
all conversions. Through the input configuration regis-
ter, the analog inputs can be configured for either dif-
ferential or single-ended conversions. When sampling
signal sources close to the MAX1153/MAX1154, single-
ended conversion is generally sufficient. Single-ended
conversions use only one analog input per signal
source, internally referenced to GND.
MUX
AIN 0
VDD
AIN 1
AIN 2
AIN 3
AIN 4
AIN 5
AIN 6
AIN 7
TEMP
SENSE
12-BIT
ADC WITH T/H
DIGITAL
COMPARATOR
INPUT REGISTERS 0–10
CURRENT DATA
UPPER THRESHOLD
LOWER THRESHOLD
# FAULT CYCLES
AVERAGE
CONFIGURATION/
STATUS
REGISTERS
SCAN AND
CONVERSION
CONTROL
SERIAL
INTERFACE
DIN
INT
DOUT
SCLK
CS
Figure 3. Simplified Alarm Block Diagram of the MAX1153/MAX1154
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