MAX1153/MAX1154
Stand-Alone, 10-Channel, 10-Bit System Monitors
with Internal Temperature Sensor and VDD Monitor
16
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Read Alarm Register
(Command Code 0001)
The Read Alarm Register command, 0001, outputs the
current status of the alarm register (see Table 11). The
address bits in this command are ignored. The alarm
register is 24 bits long and outputs in 3 bytes. Table 12
illustrates the encoding of the alarm register.
After receiving an interrupt, read the alarm register to
determine the source of the interrupt (see the
Alarm
Register section).
Read Current Data Register for Selected
Channel (Command Code 0010)
The Read Current Data Register for Selected Channel
command, 0010, outputs the data in the current data
register of the selected channel. The address bits fol-
lowing this command select the input channel to be
read (see Table 3). The current data register is a 10-bit
register. It takes 2 bytes to read its value. See the
Output Data Format and Current Data Registers sec-
tions for more details. See Table 3 for channel address-
es. Also, see Figure 7.
Read Current Data Register for All
Channels (Command Code 0011)
The Read Current Data Registers for All Channels com-
mand, 0011, outputs the data in the current data regis-
ters of all 10 channels, starting with the internal
temperature sensor, then the VDD monitor, followed by
AIN0 to AIN7. The address bits following this command
are ignored. It takes 20 bytes to read all of the 10 chan-
nels’ current data registers.
Read Configuration Register for Selected
Channel (Command Code 0100)
The Read Configuration Register for Selected Channel
command, 0100, outputs the configuration data of the
channel selected by the address bits (see Table 3).
The first register that shifts out is the upper threshold
register (2 bytes), followed by the lower threshold regis-
ter (2 bytes), ending with the channel configuration reg-
ister (1 byte), all MSB first. It takes 5 bytes to read all
three registers. See the
Channel Registers section for
more details.
SCLK
DIN
DOUT
C3
C2
C1 C0
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
CS
Figure 7. Serial Register Read Timing