參數(shù)資料
型號: MAX11206EEE+T
廠商: Maxim Integrated Products
文件頁數(shù): 16/27頁
文件大小: 0K
描述: IC ADC 20BIT 16QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 20
采樣率(每秒): 480
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極;1 個差分,雙極
23
Maxim Integrated
20-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
MAX11206/MAX11207
SCOC: Self-Calibration Offset Register
The self-calibration offset register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB first. This register holds the self-calibration offset value. The format is always in two’s complement binary
format. A write to the self-calibration offset register is allowed. The written value remains valid until it is either rewritten
or until an on-demand self-calibration operation is performed, which overwrites the user-supplied value.
The self-calibration offset value is subtracted from each conversion result provided the NOSCO bit in the CTRL3 reg-
ister is set to 0. The self-calibration offset value is subtracted from the conversion result before the self-calibration gain
correction and before the system offset and gain correction. The self-calibration offset value is also applied prior to the
2x scale factor associated with unipolar mode.
Table 18. SGC Register (Read/Write)
Table 19. SCOC Register (Read/Write)
SGC: System Gain Calibration Register
The system gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB first. This register holds the system gain calibration value. The format is always in two’s complement binary
format. A write to the system-calibration register is allowed. The written value remains valid until it is either rewritten or
until an on-demand system-calibration operation is performed, which overwrites the user-supplied value.
The system gain calibration value is used to scale the offset corrected conversion result, provided the NOSYSG bit
in the CTRL3 register is set to 0. The system gain calibration value scales the offset-corrected result by up to 2x or
corrects a gain error of approximately -50%. The amount of positive gain error that can be corrected is determined by
modulator overload characteristics, which can be as much as +25%. The gain is corrected to within 2 LSB.
BIT
B23
B22
B21
B20
B19
B18
B17
B16
DEFAULT
0
BIT
B15
B14
B13
B12
B11
B10
B9
B8
DEFAULT
0
BIT
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0
BIT
B23
B22
B21
B20
B19
B18
B17
B16
DEFAULT
0
BIT
B15
B14
B13
B12
B11
B10
B9
B8
DEFAULT
0
BIT
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0
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