參數(shù)資料
型號: MAX11205BEUB+
廠商: Maxim Integrated Products
文件頁數(shù): 9/14頁
文件大?。?/td> 0K
描述: IC ADC 16BIT SRL 1CH 10-UMAX
標(biāo)準(zhǔn)包裝: 50
位數(shù): 16
采樣率(每秒): 13.75
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 444mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-uMAX
包裝: 管件
輸入數(shù)目和類型: 1 個差分,雙極
4 ______________________________________________________________________________________
MAX11205
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: VAINP = VAINN.
Note 4: ppmFSR is parts per million of full-scale range.
Note 5: Positive full-scale error includes zero-scale errors.
Note 6: Tested with VREF = 1.8V.
Note 7: The MAX11205A has no normal-mode rejection at 50Hz or 60Hz.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Rising Edge Data Hold
Time
t4
Allows for positive edge data read
3
ns
RDY/DOUT Fall to SCLK Rising
Edge
t5
0
ns
Next Data Update Time;
No Read Allowed
t6
MAX11205A
155
F
s
MAX11205B
169
Data Conversion Time
t7
MAX11205A
8.6
ms
MAX11205B
73
Data Ready Time After
Calibration Starts (CAL + CNV)
t8
MAX11205A
208.3
ms
MAX11205B
256.1
SCLK High After RDY/DOUT Goes
Low to Activate Sleep Mode
t9
MAX11205A
0
8.6
ms
MAX11205B
0
73
Time from RDY/DOUT Low to
SCLK High for Sleep Mode
Activation
t10
MAX11205A
0
8.6
ms
MAX11205B
0
73
Data Ready Time After Wake-Up
from Sleep Mode
t11
MAX11205A
8.6
ms
MAX11205B
73
Data Ready Time After
Calibration from Sleep Mode
Wake-Up (CAL + CNV)
t12
MAX11205A
208.4
ms
MAX11205B
256.2
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