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參數(shù)資料
| 型號(hào)： | MAX1112CAP+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8-BIT 50KSPS 20-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 50k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 680µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極 |
| 產(chǎn)品目錄頁面： | 1395 (CN2011-ZH PDF) |
__________Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1112/MAX1113 in internal clock mode. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. No conversions should
be performed until the reference voltage has stabilized
(see the Wakeup Time specifications in the Timing
Characteristics).
Power-Down
When operating at speeds below the maximum sam-
pling rate, the MAX1112/MAX1113’s automatic power-
down mode can save considerable power by placing
the converters in a low-current shutdown state between
conversions. Figure 13 shows the average supply cur-
rent as a function of the sampling rate.
Select power-down with PD1 of the DIN control byte
with SHDN high or high impedance (Table 3). Pull
SHDN low at any time to shut down the converters com-
pletely. SHDN overrides PD1 of the control byte.
Figures 14a and 14b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bit PD1 of the
control byte. When software power-down is asserted, the
ADCs continue to operate in the last specified clock
mode until the conversion is complete. The ADCs then
power down into a low quiescent-current state. In internal
clock mode, the interface remains active, and conversion
results can be clocked out after the MAX1112/
MAX1113 have entered a software power-down.
The first logical 1 on DIN is interpreted as a start bit,
which powers up the MAX1112/MAX1113. If the DIN byte
contains PD1 = 1, then the chip remains powered up. If
PD1 = 0, power-down resumes after one conversion.
Hard-Wired Power-Down
Pulling SHDN low places the converters in hard-wired
power-down. Unlike software power-down, the conversion
is not completed; it stops coincidentally with SHDN being
brought low. SHDN also controls the state of the internal
reference (Table 5). Letting SHDN high impedance
enables the internal 4.096V voltage reference. When
returning to normal operation with SHDN high impedance,
there is a tRC delay of approximately 1M
Ω x CLOAD,
where CLOAD is the capacitive loading on the SHDN pin.
Pulling SHDN high disables the internal reference, which
saves power when using an external reference.
External Reference
An external reference between 1V and VDD should be
connected directly at the REFIN terminal. The DC input
impedance at REFIN is extremely high, consisting of
leakage current only (typically 10nA). During a conver-
sion, the reference must be able to deliver up to 20A
average load current and have an output impedance of
1k
Ω or less at the conversion clock frequency. If the
reference has higher output impedance or is noisy,
bypass it close to the REFIN pin with a 0.1F capacitor.
If an external reference is used with the MAX1112/
MAX1113, connect SHDN to VDD to disable the internal
reference and decrease power consumption.
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
16
______________________________________________________________________________________
Table 5. Hard-Wired Power-Down and
Internal Reference State
SHDN
STATE
DEVICE
MODE
1
Enabled
High Impedance
Enabled
0
Power-Down
INTERNAL
REFERENCE
Disabled
Enabled
1000
10
010
30
50
100
MAX1112/13-fig13
SAMPLING RATE (ksps)
SUPPLY
CURRENT
(μ
A)
20
40
VDD = VREFIN = 5V
CLOAD AT DOUT + SSTRB
CLOAD = 30pF
CODE = 11111111
CLOAD = 30pF
CODE = 10101010
CLOAD = 60pF
CODE = 10101010
Figure 13. Average Supply Current vs. Sampling Rate
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1112CAP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 5V Low-Power Multi Ch Serial 8-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1112CAP+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 5V Low-Power Multi Ch Serial 8-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1112CAP-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1112CPP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1112CPP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 5V Low-Power Multi Ch Serial 8-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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