參數(shù)資料
型號(hào): MAX110BEWE+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/24頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 2CH 16-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 14
采樣率(每秒): 50
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 762mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,雙極
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
______________________________________________________________________________________
13
CS
SCLK
tCSH
tCSS
tCK
tDH
MSB
LSB
tDS
DIN
DOUT
BUSY
tDH
tCK
tDO
tDA
POL
OFL
MSB
DO
END OF
CONVERSION
START OF
CONVERSION
Figure 6. Detailed Serial-Interface Timing
The ADC serial interface operates with just SCLK, DIN,
and DOUT (allow sufficient time for the conversion to
complete between read/write operations). Achieve con-
tinuous operation by connecting BUSY to an uncommit-
ted P I/O or interrupt, to signal the processor when the
conversion results are ready. Figures 8a and 8b show
the timing for SPI/MICROWIRE and QSPI operation.
The fully static 16-bit I/O register allows infinite time
between the two 8-bit read/write operations necessary
to obtain the full 16 bits of data with SPI and
MICROWIRE. CS must remain low during the entire
two-byte transfer (Figure 8a). QSPI allows a full 16-bit
data transfer (Figure 8b).
Interfacing to the 80C32 Microcontroller Family
Figure 7c shows the general 80C32 connection to the
MAX110/MAX111 using Port 1. For a more detailed dis-
cussion, see the MAX110 evaluation kit manual.
I/O Shift Register
Serial data transfer is accomplished with a 16-bit fully
static shift register. The 16-bit control word shifted into
this register during a data-transfer operation controls
the ADC’s various functions. The MSB (NO-OP)
enables/disables transfer of the control word within the
ADC. A logic 1 causes the remaining 15 bits in the con-
trol word to be transferred from the I/O register into the
control register when CS goes high, updating the
ADC’s configuration and starting a new conversion. If
I/O
SCK
MISO
MOSI
MASKABLE
INTERRUPT
SS
a. SPI/QSPI
+5V
P
CS
SCLK
DOUT
DIN
BUSY
MAX110
MAX111
I/O
SK
SI
SO
MASKABLE
INTERRUPT or I/O
b. MICROWIRE
P
CS
SCLK
DOUT
DIN
BUSY
P1.0
P1.1
P1.2
P1.3
P1.4
c. 80C51/80C32
P
CS
SCLK
DIN
DOUT
BUSY
MAX110
MAX111
MAX110
MAX111
Figure 7. Common Serial-Interface Connections
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