參數(shù)資料
型號(hào): MAX1109CUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/20頁
文件大?。?/td> 0K
描述: IC ADC 8BIT LP 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 8
采樣率(每秒): 50k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 444mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極;1 個(gè)偽差分,單極;1 個(gè)偽差分,雙極
MAX1108/MAX1109
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
10
______________________________________________________________________________________
_______________Detailed Description
The MAX1108/MAX1109 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible
serial interface provides easy interface to microproces-
sors (Ps). No external hold capacitors are required. All
of the MAX1108/MAX1109 operating modes are soft-
ware-configurable: internal or external reference, inter-
nal or external conversion clock, single-ended unipolar
or pseudo-differential unipolar/bipolar conversion, and
power down (Table 1).
Analog Inputs
Track/Hold
The input architecture of the ADCs is illustrated in the
equivalent-input circuit of Figure 4 and is composed of
the T/H, the input multiplexer, the input comparator, the
switched capacitor DAC, the reference, and the auto-
zero rail.
The analog-inputs configuration is determined by the
control-byte through the serial interface as shown in
Table 2 (see Modes of Operation section and Table 1).
The eight modes of operation include single-ended,
pseudo-differential, unipolar/bipolar, and a VDD moni-
toring mode. During acquisition and conversion, only
one of the switches in Figure 4 is closed at any time.
The T/H enters its tracking mode on the falling clock
edge after bit 4 (SEL0) of the control byte has been
shifted in. It enters its hold mode on the falling edge
after the bit 2 (I/EREF) of the control byte has been
shifted in.
For example, If CH0 and COM are chosen (SEL2 =
SEL1 = SEL0 = 1) for conversion, CH0 is defined as the
sampled input (SI), and COM is defined as the refer-
ence input (RI). During acquisition mode, the CH0
switch and the T/H switch are closed, charging the
VDD
3k
CLOAD
DGND
DOUT
CLOAD
DGND
3k
DOUT
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
VDD
3k
CLOAD
DGND
DOUT
CLOAD
DGND
3k
DOUT
a) VOH to High-Z
b) VOL to High-Z
Figure 2. Load Circuits for Disable Time
VDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
DOUT
DIN
SCLK
CS
COM
GND
VDD
CH1
1
F
0.1
F
1
F
CH0
ANALOG
INPUTS
MAX1108
MAX1109
CPU
VDD
REF
Figure 3. Typical Operating Circuit
CH0
COM
VDD / 2
GND
CH1
REF
GND
CHOLD
18pF
CAPACITIVE DAC
COMPARATOR
RIN
6.5k
AUTOZERO
RAIL
TRACK
HOLD
Figure 4. Equivalent Input Circuit
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