參數(shù)資料
型號: MAX11058ECB+T
廠商: Maxim Integrated Products
文件頁數(shù): 10/25頁
文件大小: 0K
描述: IC ADC 14BIT PAR 250KSPS 64TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 250k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 6
功率耗散(最大): 3.48W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-TQFP-EP(10x10)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 6 個單端,單極
MAX11047–MAX11049/MAX11057–MAX11059
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
18
______________________________________________________________________________________
Sn
Sn + 1
t8
t12
t13
t9
t10
t11
RD
(USER SUPPLIED)
CS
(USER SUPPLIED)
DB0–DB15
Figure 5. Readout Timing Requirements
Figure 4. Programming Configuration-Register Timing Requirements
Bypass AVDD and DVDD to the ground plane with
0.1F ceramic chip capacitors on each pin as close as
possible to the device to minimize parasitic inductance.
Add at least one bulk 10F decoupling capacitor to
AVDD and DVDD per PCB. Interconnect all of the
AVDD inputs and DVDD inputs using two solid power
planes. For best performance, bring the AVDD power
plane in on the analog interface side of the devices and
the DVDD power plane from the digital interface side of
the devices.
For sampling periods near minimum (1s) use a 1nF
C0G ceramic chip capacitor between each of the chan-
nel inputs to the ground plane as close as possible to the
devices. This capacitor reduces the inductance seen by
the sampling circuitry and reduces the voltage transient
seen by the input source circuit.
CONFIGURATION
REGISTER
t6
t3
t4
t5
t7
WR
(USER SUPPLIED)
CS
(USER SUPPLIED)
CR0–CR3
(USER SUPPLIED)
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