- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10492 > MAX11040KGUU+ (Maxim Integrated Products)IC ADC 24BIT 4CH 38-TSSOP PDF資料下載
參數(shù)資料
| 型號： | MAX11040KGUU+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 4CH 38-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.07M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 功率耗散（最大）： | 1.1W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 38-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
19
Maxim Integrated
Sampling Instant Control Register
By default, the devices sample all 4 input channels
simultaneously. To delay the sampling instant on one or
more channels, program the appropriate byte in the
Sampling Instant Control register. The delay of the
actual sampling instant of each individual channel from
the default sampling instant (PHI_[7:0] = 0x00) is
adjustable between 32 to 819,121 XIN clock cycles,
which is 1.3μs to 333μs with fXINCLOCK at 24.576MHz
(see Table 3.)
Configuration Register
The Configuration register contains 5 bits that control the
functionality of the devices. The default state is 0x00.
The data length of the Configuration register is 8 bits
per cascaded device (see Table 4).
Table 3. Sampling Instant Control Register
BIT
NAME
DESCRIPTION
[31:24]
PHI0[7:0]
Channel 0 sample instant adjust. PHI0 delays sampling instant on channel 0 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).
[23:16]
PHI1[7:0]
Channel 1 sample instant adjust. PHI1 delays sampling instant on channel 1 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).
[15:8]
PHI2[7:0]
Channel 2 sample instant adjust. PHI2 delays sampling instant on channel 2 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).
[7:0]
PHI3[7:0]
Channel 3 sample instant adjust. PHI3 delays sampling instant on channel 3 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).
Table 4. Configuration Register
BIT
NAME
DESCRIPTION
7
SHDN
Shutdown bit. Set SHDN high to place the device in shutdown mode. In shutdown mode, the internal
oscillator, fault circuitry, and internal bandgap reference are turned off. Set SHDN low for normal operation.
6
RST
Reset bit. Set RST high to reset all registers to the default states except for the RST bit, and realign
sampling clocks and output data.
5
EN24BIT
Enable 24-bit resolution bit for the MAX11040K. Set EN24BIT high to enable the 24-bit data output. Set
EN24BIT low to enable 19-bit data output with device address and channel address tags. Tables 5 and 6
specify the Data register for both states of this bit. Set to 0 for MAX11060.
4
XTALEN
Internal oscillator enable bit. When using the on-chip crystal oscillator as the clock source, set XTALEN high
to enable the crystal oscillator and provide a buffered version of the crystal clock at the CLKOUT output.
When using an external clock source, set XTALEN low to disable the internal crystal oscillator and three-
state the CLKOUT output. Connect the external clock source to the XIN input.
3
FAULTDIS
Overvoltage fault-protection disable bit. Set FAULTDIS high to disable the overvoltage fault-protection
circuits. For FAULTDIS = 0, the absolute maximum input range is ±6V. Analog inputs beyond the fault-
detection threshold range trip the fault-protection circuits. The output remains clipped for a fault-recovery
time (typically < 1.57ms) after the inputs return within the fault-detection threshold range. For FAULTDIS =
1, the absolute maximum input range is only ±3.5V, but there is no fault-recovery delay. See the
Overvoltage Fault Detection and Recovery (FAULT) section.
2
PDBUF
PDBUF = 1 disables the internal reference buffer. Use this mode when an external reference is used;
otherwise, PDBUF should be set to 0 to enable the internal reference buffer.
[1:0]
Reserved
Must set to 0.
相關PDF資料 |
PDF描述 |
|---|---|
| UP050SL100J-A-B | CAP CER 10PF 50V 5% AXIAL |
| ICL7109CMH+D | IC ADC 12BIT 3-ST 44-MQFP |
| DS26303LN-120+ | IC LIU E1/T1/J1 3.3V 144-ELQFP |
| MS3116P10-98S | CONN PLUG 6POS STRAIGHT W/SCKT |
| MAX132CNG+ | IC ADC 18BIT W/SRL INTRFC 24-DIP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX11040KGUU/GG8 | 制造商:Maxim Integrated Products 功能描述:24-BIT, 4-CHANNEL, SIMULTANEOUS-SAMPLING, CASCADABLE, SIGMA- - Rail/Tube |
| MAX11040KGUU/GH9 | 制造商:Maxim Integrated Products 功能描述:24-BIT, 4-CHANNEL, SIMULTANEOUS-SAMPLING, CASCADABLE, SIGMA- - Rail/Tube |
| MAX11040KGUU+ | 功能描述:模數(shù)轉換器 - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11040KGUU+T | 功能描述:模數(shù)轉換器 - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11041 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Wired Remote Controllers |
發(fā)布緊急采購，3分鐘左右您將得到回復。