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參數(shù)資料
| 型號(hào)： | MAX1101 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA |
| 中文描述： | 單芯片，8位數(shù)字化儀與防治荒漠化公約鉗位和6位美國(guó)PGA |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | MAX1101 |
M
S ingle-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
REFBIAS
= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1μF, C
EXT
= 47nF, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
V
1.5
10
V
IL
I
IL
V
OH
V
OL
I
OL
Digital Input Voltage Low
Digital Input Leakage Current
Digital Output Voltage High
Digital Output Voltage Low
Digital Output Leakage Current
DIGITAL TIMING SPECIFICATIONS
(t
r
r
, t
f
≤
10ns, C
L
≤
50pF, unless otherwise noted)
V
3.5
V
IH
Digital Input Voltage High
mA
20
40
I
DD
Supply Current
DIGITAL INPUTS/OUTPUTS
dB
48
60
PSRR
PSRR, PGA and ADC
V
4.75
5
5.25
V
DD
Positive Supply-Voltage Range
V
0.49
0.50
0.51
V
REF-
Negative Reference Voltage
POWER SUPPLIES
V
2.94
3.00
3.06
V
REF+
Positive Reference Voltage
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Internally generated, V
REFBIAS
= 5V
Internally generated, V
REFBIAS
= 5V
4.75V
≤
V
DD
≤
5.25V
CONDITIONS
-10
μA
V
V
μA
I
SOURCE
= 4mA
I
SINK
= 4mA
Output in high-impedance mode
V
DD
- 0.5
0.5
10
-10
SCLK Frequency
SCLK Pulse Width
f
SCLK
t
SPW
10
MHz
ns
VIDSAMP Pulse Width
VIDSAMP to CLAMP Separation
LOAD Pulse Width
VIDSAMP Fall to SCLK Rise Time
VIDSAMP Fall to DATA
VIDSAMP to Reset Separation
t
VS
t
VB
t
LD
t
VLS
t
VLD
t
VR
500
50
50
50
ns
ns
ns
ns
ns
ns
MODE = 1
MODE = 1
(Note 2)
60
SCLK Rise to DATA
DATA Set-Up Time
DATA Hold Time
LOAD Fall to SCLK Rise Time
SCLK Rise to LOAD Rise Time
MODE Setup Time
CLAMP Pulse Width
CLAMP Fall to Video Update
Digital Quiet Time (Note 3)
t
SD
t
DSU
t
DH
t
LS
t
SL
t
MSU
t
BS
t
BC
t
Q
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
50
50
50
300
20
20
MODE = 0
MODE = 0
Same as bus-relinquish time
(Note 1)
± around VIDSAMP falling edge
50
Reset to CLAMP Separation
t
RB
(Note 2)
50
ns
Note 1:
Due to leakage in the PGA and ADC, operation at sample rates below 1ksps is not recommended, as
performance may degrade, particularly at high temperatures.
Note 2:
Production test equipment settling time prohibits leakage measurements below 1nA.
Lab equipment has shown the MAX1101 switch input leakage below 1pA at T
A
= +25°C, and below 50pA at T
A
= +70°C.
Note 3:
Not a test parameter. Recommended for optimal performance.
50
REFERENCE VOLTAGE INPUT
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