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    參數(shù)資料
    型號(hào): MAX1090AEEI+T
    廠商: Maxim Integrated Products
    文件頁數(shù): 20/20頁
    文件大?。?/td> 0K
    描述: IC ADC 10BIT 400KSPS 28-QSOP
    產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
    Obsolescence Mitigation Program
    標(biāo)準(zhǔn)包裝: 2,500
    位數(shù): 10
    采樣率(每秒): 400k
    數(shù)據(jù)接口: 并聯(lián)
    轉(zhuǎn)換器數(shù)目: 1
    功率耗散(最大): 667mW
    電壓電源: 單電源
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 28-SSOP(0.154",3.90mm 寬)
    供應(yīng)商設(shè)備封裝: 28-QSOP
    包裝: 帶卷 (TR)
    輸入數(shù)目和類型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)偽差分,單極;4 個(gè)偽差分,雙極
    MAX1090/MAX1092
    400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
    with +2.5V Reference and Parallel Interface
    _______________________________________________________________________________________
    9
    Detailed Description
    Converter Operation
    The MAX1090/MAX1092 ADCs use a successive-
    approximation (SAR) conversion technique and an input
    track-and-hold (T/H) stage to convert an analog input
    signal to a 10-bit digital output. Their parallel (8 + 2) out-
    put format provides an easy interface to standard micro-
    processors (Ps). Figure 2 shows the simplified internal
    architecture of the MAX1090/MAX1092.
    Single-Ended and
    Pseudo-Differential Operation
    The sampling architecture of the ADC’s analog com-
    parator is illustrated in the equivalent input circuits in
    Figures 3a and 3b. In single-ended mode, IN+ is inter-
    nally switched to channels CH0–CH7 for the MAX1090
    (Figure 3a) and to CH0–CH3 for the MAX1092 (Figure
    3b), while IN- is switched to COM (Table 3). In differen-
    tial mode, IN+ and IN- are selected from analog input
    pairs (Table 4).
    In differential mode, IN- and IN+ are internally switched to
    either of the analog inputs. This configuration is pseudo-
    differential in that only the signal at IN+ is sampled. The
    return side (IN-) must remain stable within ±0.5 LSB
    (±0.1 LSB for best performance) with respect to GND
    during a conversion. To accomplish this, connect a
    0.1F capacitor from IN- (the selected input) to GND.
    During the acquisition interval, the channel selected as
    the positive input (IN+) charges capacitor CHOLD. At
    the end of the acquisition interval, the T/H switch
    opens, retaining the charge on CHOLD as a sample of
    the signal at IN+.
    The conversion interval begins with the input multiplex-
    er switching CHOLD from the positive input (IN+) to the
    negative input (IN-). This unbalances node ZERO at the
    comparator’s positive input. The capacitive digital-to-
    analog converter (DAC) adjusts during the remainder of
    the conversion cycle to restore node ZERO to 0V within
    the limits of 10-bit resolution. This action is equivalent to
    transferring a 12pF [(VIN+) - (VIN-)] charge from CHOLD
    to the binary-weighted capacitive DAC, which in turn
    forms a digital representation of the analog input signal.
    T/H
    THREE-STATE, BIDIRECTIONAL
    I/O INTERFACE
    10
    17k
    8
    2
    8
    2
    8
    SUCCESSIVE-
    APPROXIMATION
    REGISTER
    MUX
    ( ) ARE FOR MAX1090 ONLY.
    CHARGE REDISTRIBUTION
    10-BIT DAC
    CLOCK
    ANALOG
    INPUT
    MULTIPLEXER
    CONTROL LOGIC
    AND
    LATCHES
    REF
    REFADJ
    1.22V
    REFERENCE
    D0–D7
    8-BIT DATA BUS
    (CH5)
    (CH4)
    CH3
    CH2
    CH1
    CH0
    COM
    CLK
    CS
    WR
    RD
    INT
    VDD
    HBEN
    GND
    VLOGIC
    MAX1090
    MAX1092
    AV =
    2.05
    COMP
    (CH7)
    (CH6)
    Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1090/MAX1092
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