- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9924 > MAX1083BEUE+T (Maxim Integrated Products)IC ADC 10BIT 300KSPS 16-TSSOP PDF資料下載
參數(shù)資料
| 型號： | MAX1083BEUE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/23頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 300KSPS 16-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 300k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 533mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
MAX1082/MAX1083
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 10-Bit ADCs with Internal Reference
13
Maxim Integrated
Serial Clock
The external clock not only shifts data in and out, but it
also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the
next 12 SCLK falling edges, MSB first (Figure 5). SSTRB
and DOUT go into a high-impedance state when CS
goes high; after the next CS falling edge, SSTRB out-
puts a logic low. Figure 6 shows the detailed serial-inter-
face timings.
The conversion must complete in 120s or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Data Framing
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after VDD1 and VDD2
are applied.
OR
The first high bit clocked into DIN after bit B4 of a
conversion in progress is clocked onto the DOUT pin
(Figure 7).
Once a start bit has been recognized, the current conver-
sion may only be terminated by pulling SHDN low.
The fastest the MAX1082/MAX1083 can run with CS held
low between conversions is 16 clocks per conversion.
Figure 7 shows the serial-interface timing necessary to
perform a conversion every 16 SCLK cycles. If CS is tied
low and SCLK is continuous, guarantee a start bit by first
clocking in 16 zeros.
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1082/MAX1083 in normal operating mode, ready to
convert with SSTRB = low. After the power supplies sta-
bilize, the internal reset time is 10s, and no conver-
sions should be performed during this phase. If CS is
low, the first logic 1 on DIN is interpreted as a start bit.
Until a conversion takes place, DOUT shifts out zeros.
Additionally, wait for the reference to stabilize when
using the internal reference.
Power Modes
Save power by placing the converter in one of two low-
current operating modes or in full power-down between
conversions. Select the power mode through bit 1 and
bit 0 of the DIN control byte (Tables 3 and 4), or force
the converter into hardware shutdown by driving SHDN
to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
progress. In software power-down mode, the serial
interface remains active while waiting for a new control
byte to start conversion and switch to full-power mode.
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
COM
00
1
+
–
10
1
+
–
01
0
+
–
11
0
+
–
Table 1. Channel Selection in Single-Ended Mode (SGL/
DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
00
1
+
–
01
0
+
–
10
1
–
+
11
0
–
+
Table 2. Channel Selection in Pseudo-Differential Mode (SGL/
DIF = 0)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72V2103L15PF8 | IC FIFO SUPERSYNCII 15NS 80-TQFP |
| MS27656T15F15PD | CONN RCPT 15POS WALL MNT W/PINS |
| IDT72V2101L20PF8 | IC FIFO SS 131X18 20NS 64QFP |
| MAX1082ACUE+T | IC ADC 10BIT 400KSPS 16-TSSOP |
| IDT72V2101L15PF8 | IC FIFO SS 131X18 15NS 64QFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1084 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:400ksps/300ksps, Single-Supply, Low-Power, Serial 10-Bit ADCs with Internal Reference |
| MAX1084ACSA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1084ACSA+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 300/400ksps Sgl-Sply 4Ch Serial 10Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1084ACSA+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 300/400ksps Sgl-Sply 4Ch Serial 10Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1084ACSA-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。