參數(shù)資料
型號(hào): MAX1083ACUE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/23頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 300KSPS 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
采樣率(每秒): 300k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 533mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;4 個(gè)單端,雙極;2 個(gè)差分,單極;2 個(gè)差分,雙極
MAX1082/MAX1083
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 10-Bit ADCs with Internal Reference
15
Maxim Integrated
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software power-down is
asserted, the ADC completes the conversion in
progress and powers down into the specified low-qui-
escent-current state (2A, 0.9mA, or 1.3mA).
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1082/MAX1083 into its full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 = 1, a
0.9mA power-down resumes after one conversion.
Table 4 details the four power modes with the corre-
sponding supply current and operating sections.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. When returning to normal
operation—from SHDN, with an external reference—the
MAX1082/MAX1083 can be considered fully powered
up within 2s of actively pulling SHDN high. When
using the internal reference, the conversion should be
initiated only when the reference has settled; its recov-
ery time is dependent on the external bypass capaci-
tors and the time between conversions.
Power-Down Sequencing
The MAX1082/MAX1083 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 9 and 10 show the
average supply current as a function of the sampling
rate. The following sections discuss the various power-
down sequences. Other combinations of clock rates
and power-down modes may attain the lowest power
consumption in other applications.
Using Full Power-Down Mode
Full power-down mode (FULLPD) achieves the lowest
power consumption, up to 1000 conversions per chan-
nel per second. Figure 9a shows the MAX1083’s power
consumption for one- or four-channel conversions utiliz-
ing full power-down mode (PD1 = PD0 = 0), with the
internal reference and conversion controlled at the
maximum clock speed. A 0.01F bypass capacitor at
REFADJ forms an RC filter with the internal 17k
refer-
ence resistor, with a 170s time constant. To achieve
full 10-bit accuracy, seven time constants or 1.2ms are
required after power-up if the bypass capacitor is fully
discharged between conversions. Waiting this 1.2ms
duration in fast power-down (FASTPD) or reduced-
power (REDP) mode instead of in full power-up can fur-
ther reduce power consumption. This is achieved by
using the sequence shown in Figure 11a.
Figure 9b shows the MAX1083’s power consumption for
one- or four-channel conversions utilizing FULLPD
400ns
(CLK = 6.4MHz)
IDLE
CS
SCLK
DIN
SSTRB
DOUT
A/D STATE
tACQ
IDLE
CONVERSION
RB3
RB2
RB1
SEL
2
1
START
4
8
9
1216
2024
SEL
1
SEL
0
UNI/
BIP
SGL/
DIF
PD2 PD2
B9 B8
B7
B6 B5
B4
B3
B2
B1 B0
S1
S0
Figure 5. Single-Conversion Timing
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