
M
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 10-Bit ADCs with Internal Reference
6
_______________________________________________________________________________________
V
DD1
=
V
DD2
=
3.6V
I
SOURCE
= 0.5mA
CS
= V
DD2
CS
= V
DD2
V
DD1
= V
DD2
= 2.7V to 3.6V, midscale input
CONDITIONS
mA
2.5
1.3
0.9
2.0
±0.5
3.5
2.0
1.5
1.0
±2.0
IV
DD1
+ IV
DD2
Supply Current
V
2.7
3.6
V
DD1,
V
DD2
V
V
DD2
- 0.5V
V
OH
I
L
C
OUT
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLY
Positive Supply Voltage
(Note 9)
Normal operating mode (Note 10)
Reduced-power mode (Note 11)
Fast power-down mode (Note 11)
Full power-down mode (Note 11)
μA
mV
PSR
Power-Supply Rejection
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
I
SINK
= 5mA
V
0.4
V
OL
Output Voltage Low
μA
pF
±10
15
ELECTRICAL CHARACTERISTICS—MAX1083 (continued)
(V
DD1
= V
DD2
= +2.7V to +3.6V, COM = GND, f
OSC
= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = V
DD1
, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
TIMING CHARACTERISTICS—MAX1082
(Figures 1, 2, 5, 6; V
DD1
= V
DD2
= +4.5V to +5.5V; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
CONDITIONS
ns
100
t
CSW
CS
Pulse Width High
ns
65
t
STE
CS
Fall to SSTRB Enable
ns
65
t
DOE
CS
Fall to DOUT Enable
ns
10
65
t
STD
CS
Rise to SSTRB Disable
ns
10
65
t
DOD
CS
Rise to DOUT Disable
ns
80
t
STV
SCLK Rise to SSTRB Valid
ns
80
t
DOV
SCLK Rise to DOUT Valid
ns
ns
ns
ns
ns
62
35
0
35
0
t
CL
t
DS
t
DH
t
CSS
t
CSH
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
CS
Fall to SCLK Rise Setup
SCLK Rise to
CS
Rise Hold
ns
62
t
CH
ns
156
t
CP
SCLK Period
SCLK Pulse Width High
ns
10
20
t
STH
SCLK Rise to SSTRB Hold
ns
10
20
t
DOH
SCLK Rise to DOUT Hold
ns
35
t
CS1
CS
Rise to SCLK Rise Ignore
ns
35
t
CSO
SCLK Rise to
CS
Fall Ignore
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
DIGITAL OUTPUTS
(DOUT, SSTRB)