參數(shù)資料
型號(hào): MAX1079CTC+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 13/18頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 1.5MSPS 12-TQFN
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
采樣率(每秒): 1.5M
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 22mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 12-WQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 12-TQFN-EP(4x4)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,雙極
MAX1077/MAX1079
1.5Msps, Single-Supply, Low-Power, True-
Differential, 10-Bit ADCs with Internal Reference
4
_______________________________________________________________________________________
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: 1.5Msps operation guaranteed for VL > 2.7V. See the Typical Operating Characteristics section for recommended sampling
speeds for VL < 2.7V.
Note 8: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL = VDD, fSCLK = 24MHz, 50% duty cycle, TA = -40°C to +85°C, unless otherwise noted. Typical values are
at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VL = 2.7V to VDD
18.7
SCLK Pulse-Width High
tCH
VL = 1.8V to VDD, minimum recommended
(Note 7)
22.5
ns
VL = 2.7V to VDD
18.7
SCLK Pulse-Width Low
tCL
VL = 1.8V to VDD, minimum recommended
(Note 7)
22.5
ns
CL = 30pF, VL = 2.7V to VDD
17
SCLK Rise to DOUT Transition
tDOUT
CL = 30pF, VL = 1.8V to VDD
24
ns
DOUT Remains Valid After SCLK
tDHOLD
VL = 1.8V to VDD
4ns
CNVST Fall to SCLK Fall
tSETUP
VL = 1.8V to VDD
10
ns
CNVST Pulse Width
tCSW
VL = 1.8V to VDD
20
ns
Power-Up Time; Full Power-Down
tPWR-UP
2ms
Restart Time; Partial Power-Down
tRCV
16
Cycles
CNVST
SCLK
DOUT
tDHOLD
tDOUT
tSETUP
tCSW
tCL
tCH
Figure 1. Detailed Serial-Interface Timing
GND
6k
CL
DOUT
CL
GND
VL
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
6k
Figure 2. Load Circuits for Enable/Disable Times
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