參數(shù)資料
型號(hào): MAX1069BEUD+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 15/20頁(yè)
文件大小: 0K
描述: IC ADC 14BIT I2C 58KSPS 14-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 14
采樣率(每秒): 58k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 12.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external
reference applied to REF, REFADJ = AVDD, CREF = 10F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND)
Analog Supply Voltage
VAVDD
4.75
5.25
V
Digital Supply Voltage
VDVDD
2.7
5.5
V
fSAMPLE = 58.6ksps
1.8
2.5
fSAMPLE = 10ksps
0.7
mA
fSAMPLE = 1ksps
40
Internal reference
(powered down
between conversions,
R/W = 0)
Shutdown
0.4
5.0
A
fSAMPLE = 58.6ksps
1.8
2.5
fSAMPLE = 10ksps
1.4
fSAMPLE = 1ksps
1.1
mA
Internal reference
(always on, R/W = 1)
Shutdown
0.4
5
A
fSAMPLE = 58.6ksps
0.90
1.8
fSAMPLE = 10ksps
0.36
mA
fSAMPLE = 1ksps
40
Analog Supply Current
IAVDD
External reference
(REFADJ = AVDD)
Shutdown
0.4
5
A
fSAMPLE = 58.6ksps
260
400
fSAMPLE = 10ksps
65
fSAMPLE = 1ksps
6
Digital Supply Current
IDVDD
Shutdown
0.2
5
A
Power-Supply Rejection Ratio
PSRR
VAVDD = 5V ±5%, full-scale input (Note 8)
2
6
LSB/V
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2)
Serial Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
s
Hold Time for Start Condition
tHD,STA
0.6
s
Low Period of the SCL Clock
tLOW
1.3
s
High Period of the SCL Clock
tHIGH
0.6
s
Setup Time for a Repeated
START Condition (Sr)
tSU,STA
0.6
s
Data Hold Time
tHD,DAT
(Note 9)
0
900
ns
Data Setup Time
tSU,DAT
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Note 10)
20 +
0.1CB
300
ns
Fall Time of SDA Transmitting
tF
(Note 10)
20 +
0.1CB
300
ns
Setup Time for STOP Condition
tSU,STO
0.6
s
Capacitive Load for Each Bus
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
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