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參數(shù)資料
| 型號(hào)： | MAX1069BEUD+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT I2C 58KSPS 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 58k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
for fSCL = 1.7MHz. RSOURCE is calculated with the fol-
lowing equation:
where RSOURCE is the analog input source impedance,
fSCL is the maximum system SCL frequency, N is 14
(the number of bits of resolution), CIN is 35pF (the sum
of CT/H and input stray capacitance), and RIN is 800
(the T/H switch resistances).
To improve the input-signal bandwidth under AC
conditions, drive AIN with a wideband buffer
(> 4MHz) that can drive the ADC’s input capacitance
and settle quickly (see the
Input Buffer section).
An RC filter at AIN reduces the input track-and-hold
switching transient by providing charge for CT/H.
Analog Input Bandwidth
The MAX1069 features input-tracking circuitry with a
4MHz small-signal bandwidth. The 4MHz input band-
width makes it possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. Use anti-alias filtering to avoid
high-frequency signals being aliased into the frequency
band of interest.
Analog Input Range and Protection
Internal ESD (electrostatic discharge) protection diodes
clamp AIN, REF, and REFADJ to AVDD and
AGNDS/AGND (Figure 6). These diodes allow the ana-
log inputs to swing from (VAGND - 0.3V) to (VAVDD +
0.3V) without causing damage to the device. For accu-
rate conversions, the inputs must not go more than
50mV beyond their rails.
If the analog inputs exceed 300mV beyond their
rails, limit the current to 2mA.
Internal Clock
The MAX1069 contains an internal 4MHz oscillator that
drives the SAR conversion clock. During conversion, SCL
is held low (clock stretching). An internal register stores
data when the conversion is in progress. When the
MAX1069 releases SCL, the master reads the conversion
results at any clock rate up to 1.7MHz (Figure 11).
Digital Interface
The MAX1069 features an I2C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX1069 and the master at rates up to 1.7MHz. The
master (typically a microcontroller) initiates data trans-
fer on the bus and generates SCL.
SDA and SCL require pullup resistors (500
or greater,
Figure 4). Optional resistors (24
) in series with SDA
and SCL protect the device inputs from high-voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX1069. The data on SDA must
remain stable during the high period of the SCL clock
pulse as changes in SDA while SCL is high are control
signals (see the
START and STOP Conditions section).
Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP con-
dition (P), a low-to-high transition on SDA while SCL is
high (Figure 7). The STOP condition frees the bus and
places all devices in F/S mode (see the
Bus Timing
section). Use a repeated START condition (Sr) in place
R
fIn(22 ) C
R
SOURCE
SCL
N
IN
≤
××
×
2
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
______________________________________________________________________________________
13
Figure 5. Equivalent Input Circuit
CT/H
AIN
AGNDS
CAPACITIVE
DAC
REF
TRACK
HOLD
TRACK
HOLD
TRACK
*RSOURCE
ANALOG
SIGNAL
SOURCE
*MINIMIZE RSOURCE TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (CT/H) TO
CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (tACQ).
MAX1069
Figure 6. Internal Protection Diodes
AIN
REFADJ
AVDD
AGND
REF
AGNDS
MAX1069
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1069BEUD+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 58.6ksps 14-Bit 2-Wire Serial RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1069BEUD+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 58.6ksps 14-Bit 2-Wire Serial RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1069BEUD-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1069CCUD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1069CCUD+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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