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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MAX105ECS+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 11/21闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 6BIT 800MSPS DL 80TQFP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 浣嶆暩(sh霉)锛� | 6 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 800M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 2 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 2.6W |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 80-TQFP 瑁搁湶鐒婄洡(p谩n) |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 80-TQFP-EP锛�12x12锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤�(l猫i)鍨嬶細 | 4 鍊�(g猫)鍠锛屽柈妤�锛�2 鍊�(g猫)宸垎锛屽柈妤� |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)鐣�(d膩ng)鍓嶇11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)
clock design limits aperture jitter to typically 1.5psRMS.
Figure 11 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC鈥檚 reso-
lution (N-Bits):
SNRMAX[dB] = 6.02dB x N + 1.76dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter
(see Aperture Uncertainties). SNR is computed by tak-
ing the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first four harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency, amplitude, and sampling
rate relative to an ideal ADC鈥檚 quantization noise. For a
full-scale input ENOB is computed from:
ENOB = (SINAD - 1.76dB) / 6.02dB
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1 is the fundamental amplitude, and V
2 through
V
5 are the amplitudes of the 2nd- through 5th-order har-
monics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental to the RMS value of the
next largest spurious component, excluding DC offset.
Two-Tone Intermodulation
Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are at -7dB full-scale and their envelope peaks at -1dB
full-scale.
Chip Information
TRANSISTOR COUNT: 12,286
THD
x
V
=+
+
20
2
3
2
4
2
5
2
1
2
log (
) /
)
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
______________________________________________________________________________________
19
CLK+
ANALOG
INPUT
SAMPLING
INSTANT
tAW
tAD
tAJ
CLK-
tAW: APERTURE WIDTH
tAJ: APERTURE JITTER
tAD: APERTURE DELAY
MAX105
Figure 11. Aperture Timing
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MAX1063AEEG+ | IC ADC 10BIT 250KSPS 24-QSOP |
| MAX107ECS+ | IC ADC 6BIT 400MSPS DL 80-TQFP |
| MAX1080AEUP+ | IC ADC 10BIT 400KSPS 20-TSSOP |
| MAX1084AESA+ | IC ADC 10BIT 400KSPS 8-SOIC |
| MAX1093AEEG+ | IC ADC 10BIT 250KSPS 24-QSOP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX105ECS-TD | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤�(l猫i)鍨�:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤�(l猫i)鍨�:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX105EVKIT | 鍔熻兘鎻忚堪:鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻� IC 闁�(k膩i)鐧�(f膩)宸ュ叿 MAX105/7 Eval Kit RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Demonstration Kits 椤�(l猫i)鍨�:ADC 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:ADS130E08 鎺ュ彛椤�(l猫i)鍨�:SPI 宸ヤ綔闆绘簮闆诲:- 6 V to + 6 V |
| MAX106 | 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū(ch膿ng):Maxim Integrated Products 鍔熻兘鎻忚堪:銆�5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier |
| MAX1060 | 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū(ch膿ng):Maxim Integrated Products 鍔熻兘鎻忚堪:400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface |
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