B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE: tACQ + tCONV
≤ 7.6μs PER CHANNEL.
S
1
SLAVE ADDRESS
A
71 1
R
CLOCK STRETCH
NUMBER OF BITS
P or Sr
1
8
RESULT
A
1
A. SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
71
1
R
CLOCK STRETCH
A
NUMBER OF BITS
P OR Sr
1
8
RESULT 1
A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1
tCONV2
tACQ2
tCONVN
tACQN
tCONV
tACQ
1
Figure 10. Internal Clock Mode Read Cycles
SLAVE ADDRESS
RESULT 1
RESULT 2
RESULT N
tCONV1
tACQ1
tCONV2
tACQ2
tCONVN
tACQN
tCONV
tACQ
NUMBER OF BITS
1
8
A
1
S
1
A
71 1
R
S
1
A
71 1
R
P OR Sr
1
8
A
1
A
8
A
8
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
SLAVE ADDRESS
P OR Sr
RESULT
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11. External Clock Mode Read Cycles
MAX1036–MAX1039
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
16
______________________________________________________________________________________