8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 14-Bit ADCs 14 Maxim Integrated P" />
參數(shù)資料
型號(hào): MAX1033EUP+
廠商: Maxim Integrated Products
文件頁數(shù): 6/32頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SER 115KSPS 20TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 74
位數(shù): 14
采樣率(每秒): 115k
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 879mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸入數(shù)目和類型: 4 個(gè)單端,單極;4 個(gè)單端,雙極;2 個(gè)差分,單極;2 個(gè)差分,雙極
MAX1032/MAX1033
8- and 4-Channel, ±3 x VREF
Multirange Inputs, Serial 14-Bit ADCs
14
Maxim Integrated
Power Supplies
To maintain a low-noise environment, the MAX1032/
MAX1033 provide separate power supplies for each
section of circuitry. Table 1 shows the four separate
power supplies. Achieve optimal performance using
separate AVDD1, AVDD2, DVDD, and DVDDO supplies.
Alternatively, connect AVDD1, AVDD2, and DVDD
together as close to the device as possible for a conve-
nient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close to the
device as possible. Bypass each supply to the corre-
sponding ground using a 0.1μF capacitor (Table 1). If
significant low-frequency noise is present, add a 10μF
capacitor in parallel with the 0.1μF bypass capacitor.
Converter Operation
The MAX1032/MAX1033 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert
voltage signals into a 14-bit digital result. Both single-
ended and differential configurations are supported
with programmable unipolar and bipolar signal ranges.
Track-and-Hold Circuitry
The MAX1032/MAX1033 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for
each operating mode. The MAX1032/MAX1033 analog
input circuitry buffers the input signal from the sampling
capacitors, resulting in a constant analog input current
with varying input voltage (Figure 5).
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 17k
Ω input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±16.5V fault tolerant and are protect-
ed by back-to-back diodes. The summing junction volt-
age, VSJ, is a function of the channel’s input common-
mode voltage:
V
R
RR
V
R
RR
V
SJ
CM
.
=
+
×+
+
×
1
12
2 375
1
12
Table 1. MAX1032/MAX1033 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)
CIRCUIT SECTION
BYPASSING
DVDDO/DGNDO
2.7 to 5.25
0.07
Digital I/O
0.1μF to DGNDO
AVDD2/AGND2
4.75 to 5.25
13.5
Analog Circuitry
0.1μF to AGND2
AVDD1/AGND1
4.75 to 5.25
3.0
Analog Circuitry
0.1μF to AGND1
DVDD/DGND
4.75 to 5.25
0.8
Digital Control Logic and
Memory
0.1μF to DGND
Table 2. Analog Input Configuration Byte
BIT
NUMBER
NAME
DESCRIPTION
7
START
Start Bit. The first logic 1 after
CS goes low defines the beginning of the analog input configuration byte.
6C2
5C1
4C0
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
3
DIF/
SGL
Differential or Single-Ended Configuration Bit. DIF/
SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/
SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/
SGL adjusts the FSR, as shown in Table 6.
2R2
1R1
0R0
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
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