參數(shù)資料
型號(hào): MAX1030
廠商: Maxim Integrated Products, Inc.
元件分類(lèi): ADC
英文描述: 10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference
中文描述: 10位、300ksps ADC,帶有FIFO、溫度傳感器及內(nèi)置基準(zhǔn)
文件頁(yè)數(shù): 11/24頁(yè)
文件大小: 474K
代理商: MAX1030
M
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
______________________________________________________________________________________
11
Unipolar/Bipolar
Address the unipolar and bipolar registers through the
setup register (bits 1 and 0). Program a pair of analog
channels for differential operation by writing a 1 to the
appropriate bit of the bipolar or unipolar register.
Unipolar mode sets the differential input range from 0 to
V
REF
. A negative differential analog input in unipolar
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to ±V
REF
/ 2. The digital output code is binary in unipo-
lar mode and two
s complement in bipolar mode (see
the transfer function graphs, Figures 8 and 9).
In single-ended mode, the MAX1026/MAX1028/
MAX1030 always operate in unipolar mode. The analog
inputs are internally referenced to GND with a full-scale
input range from 0 to V
REF
.
True Differential Analog Input T/H
The equivalent circuit of Figure 3 shows the
MAX1026/MAX1028/MAX1030s
input architecture. In
track mode, a positive input capacitor is connected to
AIN0
AIN15 in single-ended mode (and AIN0, AIN2,
AIN4
AIN14 in differential mode). A negative input
capacitor is connected to GND in single-ended mode
(or AIN1, AIN3, AIN5
AIN15 in differential mode). For
external track-and-hold timing, use clock mode 01.
After the T/H enters hold mode, the difference between
the sampled positive and negative input voltages is
converted. The time required for the T/H to acquire an
input signal is determined by how quickly its input
capacitance is charged. If the input signal
s source
impedance is high, the required acquisition time length-
ens. The acquisition time, t
ACQ
, is the maximum time
needed for a signal to be acquired, plus the power-up
time. It is calculated by the following equation:
where R
IN
= 1.5k
, R
S
is the source impedance of the
input signal, and t
PWR
= 1μs, the power-up time of the
device. The varying power-up times are detailed in the
explanation of the clock mode conversions.
t
ACQ
is never less than 1.4μs, and any source imped-
ance below 300
does not significantly affect the
ADC
s AC performance. A high-impedance source can
be accommodated either by lengthening t
ACQ
or by
placing a 1μF capacitor between the positive and neg-
ative analog inputs.
Internal FIFO
The MAX1026/MAX1028/MAX1030 contain a FIFO
buffer that can hold up to 16 ADC results plus one tem-
perature result. This allows the ADC to handle multiple
internally clocked conversions and a temperature mea-
surement, without tying up the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by 4
leading zeros and the LSB followed by 2 sub-bits. After
each falling edge of
CS
, the oldest available byte of
data is available at DOUT, MSB first. When the FIFO is
empty, DOUT is zero.
The first 2 bytes of data read out after a temperature mea-
surement always contain the temperature result preceded
by 4 leading zeros, MSB first. If another temperature mea-
surement is performed before the first temperature result
is read out, the old measurement is overwritten by the
new result. Temperature results are in degrees Celsius
(two
s complement) at a resolution of 1/8 of a degree. See
the
Temperature Measurements
section for details on
converting the digital code to a temperature.
Internal Clock
The MAX1026/MAX1028/MAX1030 operate from an inter-
nal oscillator, which is accurate within 10% of the
4.4MHz nominal clock rate. The internal oscillator is
active in clock modes 00, 01, and 10. Read out the data
at clock speeds up to 10MHz. See Figures 4
7 for details
on timing specifications and starting a conversion.
t
x R
R
x
pF
t
AQC
S
IN
PWR
9
+
=
)
+
24
+
-
HOLD
CIN+
REF
GND
DAC
CIN-
V
DD
/2
COMPARATOR
AIN0-AIN15
(SINGLE ENDED);
AIN0, AIN2,
AIN4…AIN14
(DIFFERENTIAL)
GND
(SINGLE ENDED);
AIN1, AIN3,
AIN5…AIN15
(DIFFERENTIAL)
HOLD
HOLD
Figure 3. Equivalent Input Circuit
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