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參數(shù)資料
| 型號(hào)： | MAX101A |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | ADC |
| 英文描述： | 500Msps, 8-Bit ADC with Track/Hold |
| 中文描述： | 500Msps、8位ADC，帶有采樣/保持 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大小： | 116K |
| 代理商： | MAX101A |
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M
500Msps, 8-Bit ADC with Trac k/Hold
8
_______________________________________________________________________________________
72, 73
AIN+
75, 76
AIN-
Analog Inputs, internally terminated with 50
to ground. Full-scale linear input range is approximately
±250mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
52
TP1
Internal connection, leave pin open.
53
TP2
Internal connection, leave pin open.
54
VA
RBS
“A” side negative reference voltage sense (Note 9)
55
VA
RB
“A” side negative reference voltage input (Note 9)
65
TP5
Internal connection, leave pin open.
50
VA
RT
“A” side positive reference voltage input (Note 9)
51
VA
RTS
“A” side positive reference voltage sense (Note 9)
NAME
FUNCTION
PIN
_________________________________________________Pin Desc ription (c ontinued)
83
PH
ADJ
Phase adjustment for T/H. Normally connected to ground. A phase adjustment of approximately ±18ps
can be made by varying this pin’s bias point to optimize interleaving between sides A and B (Note 10).
66
TP6
Internal connection, leave pin open.
Note 9:
VA
RT
, VA
RB
, VB
RT
, and VB
RB
should be adjusted separately from a well bypassed reference circuit to ensure proper
amplitude and offset matching. The sense connections to each of these terminals allows precision setting of the reference
voltage. The reference ladder is similar for both converter halves (check electrical section for values). Any noise on these
terminals will severely reduce overall performance.
Note 10:
Good results are obtained by connecting the PH
ADJ
input to ground. Improve performance by applying a voltage between
±1.25V to this input. The time that the “A” T/H bridge samples relative to the time that the “B” T/H bridge samples can be
varied through a ±18ps range.
CLK
ADATA
BDATA
CLK
DCLK
DCLK
t
PD1
t
PD2
t
PD2
t
PWH
t
PWL
Figure 1. Output Timing, Normal Mode (DIV10 = OPEN)
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