參數(shù)資料
型號(hào): MACH215-15JC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: High-Density EE CMOS Programmable Logic
中文描述: EE PLD, 15 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 2/30頁
文件大?。?/td> 245K
代理商: MACH215-15JC
10
MACH215-12/15/20
16751E-6
n
From Logic
Allocator
To Switch
Matrix
To I/O
Cell
a. Combinatorial, Active High
n
From Logic
Allocator
To Switch
Matrix
To I/O
Cell
b. Combinatorial, Active Low
n
From Logic
Allocator
To Switch
Matrix
To I/O
Cell
c. D-type Register, Active High
AP
AR
DQ
d. D-type Register, Active Low
e. T-type Register, Active High
f. T-type Register, Active Low
g. Latch, Active High
h. Latch, Active Low
CLK0
Individual
Preset
Individual
Preset
Individual
Clock
AP
AR
DQ
n
From Logic
Allocator
To Switch
Matrix
To I/O
Cell
CLK0
Individual
Preset
Individual
Preset
Individual
Clock
AP
AR
TQ
n
From Logic
Allocator
To Switch
Matrix
To I/O
Cell
CLK0
Individual
Preset
Individual
Preset
Individual
Clock
AP
AR
TQ
n
From Logic
Allocator
To Switch
Matrix
To I/O
Cell
CLK0
Individual
Preset
Individual
Preset
Individual
Clock
AP
AR
LQ
AP
AR
Q
n
From Logic
Allocator
To Switch
Matrix
To I/O
Cell
CLK0
Individual
Preset
Individual
Preset
Individual
Clock
n
From Logic
Allocator
To Switch
Matrix
To I/O
Cell
CLK0
Individual
Preset
Individual
Preset
Individual
Clock
G
L
G
Figure 4. Output Macrocell Configurations
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