參數(shù)資料
型號： MAC7111CPV50
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, LQFP-144
文件頁數(shù)： 16/48頁
文件大?。?/td> 1282K
代理商： MAC7111CPV50
23
MAC7100 Microcontroller Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical Characteristics
3.10 Analog-to-Digital Converter Characteristics
Table 24 and Table 25 show conditions under which the ATD operates. The following constraints exist to
obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists because the
sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside
of this range it will effectively be clipped.
3.10.1 Factors Influencing Accuracy
Three factors — source resistance, source capacitance and current injection — have an influence on the
accuracy of the ATD.
Table 24. ATD Operating Characteristics in 5 V Range
Conditions shown in Table 6 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
M1
D Reference Potential
Low
High
VRL
VRH
VSSA
VDDA ÷ 2
—
VDDA ÷ 2
VDDA
V
M2
C Differential Reference Voltage 1
1 Full accuracy is not guaranteed when differential voltage is less than 4.50 V
VRH – VRL
4.50
5.00
5.25
V
M3
D ATD Clock Frequency
fATDCLK
0.5
—
2.0
MHz
M4
D ATD 10-bit Conversion PeriodClock Cycles 2
@ 2.0MHz fATDCLK
2 Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.
NCONV10
TCONV10
14
7
—
28
14
Cycles
s
M5
D ATD 8-bit Conversion PeriodClock Cycles 2
@ 2.0MHz fATDCLK
NCONV8
TCONV8
12
6
—
26
13
Cycles
s
M6
D Recovery Time (VDDA = 5.0 V)
tREC
——
20
s
M7
P Reference Supply current 1 ATD module enabled
IREF
——
0.375
mA
M8
P Reference Supply current 2 ATD modules enabled
IREF
——
0.750
mA
Table 25. ATD Operating Characteristics in 3.3 V Range
Conditions shown in Table 6, with VDDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted.
Num C
Rating
Symbol
Min
Typ
Max
Unit
N1
D Reference Potential
Low
High
VRL
VRH
VSSA
VDDA ÷ 2
—
VDDA ÷ 2
VDDA
V
N2
C Differential Reference Voltage 1
1 Full accuracy is not guaranteed when differential voltage is less than 3.0 V
VRH–VRL
3.0
3.3
3.6
V
N3
D ATD Clock Frequency
fATDCLK
0.5
—
2.0
MHz
N4
D ATD 10-bit Conversion PeriodClock Cycles 2
Conv, Time at 2.0MHz ATD Clock fATDCLK
2 Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.
NCONV10
TCONV10
14
7
—
28
14
Cycles
s
N5
D ATD 8-bit Conversion PeriodClock Cycles 2
Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8
TCONV8
12
6
—
26
13
Cycles
s
N6
D Recovery Time (VDDA=5.0 V)
tREC
——
20
s
N7
P Reference Supply current 1 ATD module enabled
IREF
——
0.375
mA
N8
P Reference Supply current 2 ATD modules enabled
IREF
——
0.250
mA
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