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參數(shù)資料
| 型號(hào)： | MAC7106VPV40 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, LQFP-144 |
| 文件頁數(shù)： | 6/56頁 |
| 文件大?。?/td> | 1216K |
| 代理商： | MAC7106VPV40 |
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MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Electrical Characteristics
Freescale Semiconductor
14
3.7.5
Chip Power Up and Voltage Drops
The VREG sub-modules LVI (low voltage interrupt), POR (power on reset) and LVR (low voltage reset)
handle chip power-up or drops of the supply voltage. Refer to Figure 2.
Figure 2. VREG Chip Power-up and Voltage Monitoring
3.7.6
Output Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external
DC load is allowed. Capacitive loads are specified in Table 18. Capacitors with X7R dielectricum are
required.
Table 18. VREG Recommended Load Capacitances
Rating
Symbol
Min
Typ
Max
Unit
Load Capacitance per VDD2.5 pin
1
NOTES:
1. Refer to Table 38 for the specific number of VDD2.5 pins on various packages. Each VDD2.5 pin should have the
recommended loading as described in Section 3.7.3, “Circuit Board Layout,” of the MAC7100 Microcontroller Family
Reference Manual (MAC7100RM).
CLVDD
200
220
12000
nF
Load Capacitance on VDDPLL pin
CLVDDfcPLL
90
220
5000
nF
LVI Disabled
due to LVR
VLVID
VLVRD
LVR
POR
LVI
VPORD
VLVRA
VLVIA
Time
LVI Enabled
VDDA
VDD2.5
Voltage
Note: Not to scale.
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