參數(shù)資料
型號(hào)： MAC7101CPV50
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, LQFP-144
文件頁數(shù)： 7/48頁
文件大?。?/td> 1282K
代理商： MAC7101CPV50
15
MAC7100 Microcontroller Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical Characteristics
3.8.2
PLL Filter Characteristics
The oscillator provides the reference clock for the PLL. The voltage controlled oscillator (VCO) of the PLL
is also the system clock source in self clock mode. In order to operate reliably, care must be taken to select
proper values for external loop filter components.
Figure 3. Basic PLL Functional Diagram
The procedure described below can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table 18. First, the VCO Gain at the desired VCO output frequency is
approximated by:
The phase detector relationship is given by:
ich is the current in tracking mode. The loop bandwidth fC should be chosen to fulfill the Gardner’s stability
criteria by at least a factor of 10, typical values are 50.
ζ = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above inputs the resistance can be calculated as:
The capacitance CS can now be calculated as:
The capacitance CP should be chosen in the range of:
The stabilization delays shown in Table 18 are dependant on PLL operational settings and external
component selection (for example, crystal, XFC filter).
Phase
Detector
1
REFDV+1
Kφ
fREF
VDDPLL
R
CP
CS
KV
Loop Divider
1
SYNR+1
fVCO
fOSC
1
2
fCMP
VCO
KV
K1 e
f1 fVCO
–
()
K1 1V
--------------------------
=
KΦ
ich
–
KV
=
fC
2
ζ f
ref
πζ
1
ζ
2
+
()
-----------------------------------------
1
50
------
fC
fref
450
--------------
ζ
0.9
=
()
;
<
→
<
n
fVCO
fref
------------2
synr 1
+
()
==
R
2
π nf
C
KΦ
----------------------------
=
CS
2
ζ
2
π f
C R
---------------------
0.516
fC R
--------------
ζ
0.9
=
()
;
≈
=
CS 20
÷
CP CS 10
÷
≤≤
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