參數(shù)資料
型號(hào): M95256-WMN5T
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 一百二十八分之二百五十六千位串行SPI總線的EEPROM高速時(shí)鐘
文件頁(yè)數(shù): 30/39頁(yè)
文件大小: 580K
代理商: M95256-WMN5T
M95256, M95128
30/39
Table 22. AC Characteristics (M95xxx-R)
Note: 1. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. This product is under development. For more infomation, please contact your nearest ST sales office.
4. This is preliminary data.
Test conditions specified in
Table 11.
and
Table 10.
Symbol
Alt.
Parameter
Min.
3,4
Max.
3,4
Unit
f
C
f
SCK
Clock Frequency
D.C.
2
MHz
t
SLCH
t
CSS1
S Active Setup Time
200
ns
t
SHCH
t
CSS2
S Not Active Setup Time
200
ns
t
SHSL
t
CS
S Deselect Time
200
ns
t
CHSH
t
CSH
S Active Hold Time
200
ns
t
CHSL
S Not Active Hold Time
200
ns
t
CH 1
t
CLH
Clock High Time
200
ns
t
CL 1
t
CLL
Clock Low Time
200
ns
t
CLCH 2
t
RC
Clock Rise Time
1
μs
t
CHCL 2
t
FC
Clock Fall Time
1
μs
t
DVCH
t
DSU
Data In Setup Time
40
ns
t
CHDX
t
DH
Data In Hold Time
50
ns
t
HHCH
Clock Low Hold Time after HOLD not Active
140
ns
t
HLCH
Clock Low Hold Time after HOLD Active
90
ns
t
CHHL
Clock High Set-up Time before HOLD Active
t
CH
ns
t
CHHH
Clock High Set-up Time before HOLD not Active
t
CH
ns
t
SHQZ 2
t
DIS
Output Disable Time
250
ns
t
CLQV
t
V
Clock Low to Output Valid
150
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
QLQH 2
t
RO
Output Rise Time
100
ns
t
QHQL 2
t
FO
Output Fall Time
100
ns
t
HHQV
t
LZ
HOLD High to Output Valid
100
ns
t
HLQZ 2
t
HZ
HOLD Low to Output High-Z
250
ns
t
W
t
WC
Write Time
10
ms
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