參數(shù)資料
型號: M95256-RBN6P
廠商: 意法半導體
元件分類: DRAM
英文描述: 256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 256Kbit和128Kbit的EEPROM串行SPI總線高速時鐘
文件頁數(shù): 20/39頁
文件大小: 580K
代理商: M95256-RBN6P
M95256, M95128
20/39
POWER-UP AND DELIVERY STATE
Power-up State
After Power-up, the device is in the following state:
Standby Power mode
deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be started).
not in the Hold Condition
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
Initial Delivery State
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.
相關PDF資料
PDF描述
M95256-RBN6G 256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock
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M95256-MW6T 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
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