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參數(shù)資料
| 型號： | M95256-DL6T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 一百二十八分之二百五十六千位串行SPI總線的EEPROM高速時鐘 |
| 文件頁數(shù)： | 18/39頁 |
| 文件大小： | 580K |
| 代理商： | M95256-DL6T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
M95256, M95128
18/39
Write to Memory Array (WRITE)
As shown in
Figure 13.
, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High at a byte boundary of the input data.
In the case of
Figure 13.
, this occurs after the
eighth bit of the data byte has been latched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period t
WC
(as specified in
Ta-
ble 18.
to
Table 22.
), at the end of which the Write
in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in
Figure 14.
, the next byte of input
data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the inter-
nal address counter rolls over to the beginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 64 bytes).
The instruction is not accepted, and is not execut-
ed, under the following conditions:
–
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
–
if a Write cycle is already in progress
–
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last
data byte that has been latched in)
–
if the addressed page is in the region
protected by the Block Protect (BP1 and BP0)
bits.
Figure 13. Byte Write (WRITE) Sequence
Note: The most significant address bits (b15 for the M95256, and bits b15 and b14 for the M95128) are Don’t Care.
C
D
AI01795D
S
Q
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
High Impedance
Instruction
16-Bit Address
0
7
6
5
4
3
2
0
1
Data Byte
31
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95256-D-MN3G/A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-D-MN3G/K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-D-MN3TG/A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-D-MN3TG/K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-D-MN6G/A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
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