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參數(shù)資料
| 型號： | M89 |
| 廠商： | 意法半導體 |
| 英文描述： | In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs |
| 中文描述： | 在系統(tǒng)可編程ISP的多內存和邏輯FLASHPSD系統(tǒng)的微控制器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 65K |
| 代理商： | M89 |
1/7
DATA BRIEFING
June 2000
Complete data available on Data-on-Disc CD-ROM or at www.st.com
M89 FAMILY
In-System Programmable (ISP)
Multiple-Memory and Logic FLASH+PSD Systems for MCUs
I
Single Supply Voltage:
– 5 V
±
10% for M89xxFxY
– 3 V (+20/–10%) for M89xxFxW
I
1 or2 Mbit of Primary Flash Memory (8 uniform
sectors, 16K x 8, or 32K x 8)
I
A second non-volatile memory:
– 256 Kbit (32K x 8) EEPROM (for M8913F1x)
or Flash memory (for M89x3F2x)
– 4 uniform sectors (8K x 8)
I
SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8)
I
Over 2,000 Gates of PLD: DPLD and GPLD
I
27 Reconfigurable I/O ports
I
Enhanced JTAG Serial Port
I
Programmable power management
I
Stand-by current:
– 50
μ
A for M89xxFxY
– 25
μ
A for M89xxFxW
I
High Endurance:
– 100,000 Erase/Write Cycles of FlashMemory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
Figure 1. Logic Diagram
AI02856
16
AD0-AD15
PC0-PC7
VCC
FLASH+PSD
VSS
8
PD0-PD2
3
PB0-PB7
8
PA0-PA7
8
3
CNTL0-
CNTL2
RESET
Table 1. Signal Names
PA0-PA7
Port-A
PB0-PB7
Port-B
PC0-PC7
Port-C
PC2 = Voltage Stand-by
PD0-PD2
Port-D
AD0-AD15
Address/Data
CNTL0-CNTL2
Control
RESET
Reset
V
CC
Supply Voltage
V
SS
Ground
PLCC52 (K)
PQFP52 (T)
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