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參數(shù)資料
| 型號： | M7A3P400-FG484 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| 封裝： | 1 MM PITCH, FBGA-484 |
| 文件頁數(shù)： | 211/246頁 |
| 文件大?。?/td> | 3010K |
| 代理商： | M7A3P400-FG484 |
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ProASIC3/E Flash Family FPGAs
v2.1
2-55
FIPS46-2). AES has been designed to protect sensitive
government information well into the 21st century. It
replaces the aging DES, which NIST adopted in 1977 as a
Federal Information Processing Standard used by federal
agencies to protect sensitive, unclassified information.
The 128-bit AES standard has 3.4 × 1038 possible 128-bit
key variants, and it has been estimated that it would
take 1,000 trillion years to crack 128-bit AES cipher text
using exhaustive techniques. Keys are stored (securely) in
ProASIC3 devices in nonvolatile Flash memory. All
programming
files
sent
to
the
device
can
be
authenticated by the part prior to programming to
ensure that bad programming data is not loaded into
the part that may possibly damage it. All programming
verification is performed on-chip, ensuring that the
contents of ProASIC3 devices remain secure.
ARM-enabled ProASIC3 devices do not support the AES
decryption capability.
AES decryption can also be used on the 1,024-bit
FlashROM to allow for secure remote updates of the
FlashROM contents. This allows for easy, secure support
for subscription model products. See the application
note ProASIC3/E Security for more details.
ISP
ProASIC3 devices support IEEE 1532 ISP via JTAG and
require
a
single
VPUMP voltage of 3.3 V during
programming.
In
addition,
programming
via
a
microcontroller in a target system can be achieved. See
the application note In-System Programming (ISP) in
ProASIC3/E Using FlashPro3 for more details.
JTAG 1532
ProASIC3 devices support the JTAG-based IEEE 1532
standard for ISP. As part of this support, when a ProASIC3
device is in an unprogrammed state, all user I/O pins are
disabled. This is achieved by keeping the global IO_EN
signal deactivated, which also has the effect of disabling
the input buffers. The SAMPLE/PRELOAD instruction
captures the status of pads in parallel and shifts them
out as new data is shifted in for loading into the
Boundary Scan Register. When the ProASIC3 device is in
an
unprogrammed
state,
the
SAMPLE/PRELOAD
instruction has no effect on I/O status; however, it will
continue to shift in new data to be loaded into the BSR.
Therefore, when SAMPLE/PRELOAD is used on an
unprogrammed device, the BSR will be loaded with
undefined data. Refer to the In-System Programming
(ISP) in ProASIC3/E Using FlashPro3 application note for
more details.
For JTAG timing information on setup, hold, and fall
times, refer to the FlashPro User’s Guide.
Boundary Scan
ProASIC3 devices are compatible with IEEE Standard
1149.1, which defines a hardware architecture and the
set of mechanisms for boundary scan testing. The basic
ProASIC3 boundary scan logic circuit is composed of the
TAP controller, test data registers, and instruction
register (Figure 2-41 on page 2-57). This circuit supports
all
mandatory
IEEE
1149.1
instructions
(EXTEST,
SAMPLE/PRELOAD,
and
BYPASS)
and
the
optional
IDCODE instruction (Table 2-25).
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI, TDO (test
data input and output), TMS (test mode selector), and
TRST (test reset input). TMS, TDI, and TRST are equipped
with pull-up resistors to ensure proper operation when
no input data is supplied to them. These pins are
dedicated for boundary scan test usage. Refer to the
"JTAG Pins" section on page 2-53 for pull-up/down
recommendations for TDO and TCK pins. Table 2-26 gives
pull-down recommendations for the TRST and TCK
pins.
8. The A3P030 device does not support AES decryption.
Table 2-25 Boundary Scan Opcodes
Hex Opcode
EXTEST
00
HIGHZ
07
USERCODE
0E
SAMPLE/PRELOAD
01
IDCODE
0F
CLAMP
05
BYPASS
FF
Table 2-26 TRST and TCK Pull-Down Recommendations
VJTAG
Tie-Off Resistance*
VJTAG at 3.3 V
200
Ω to 1 kΩ
VJTAG at 2.5 V
200
Ω to 1 kΩ
VJTAG at 1.8 V
500
Ω to 1 kΩ
VJTAG at 1.5 V
500
Ω to 1 kΩ
Note: *Equivalent parallel resistance if more than one device
is on JTAG chain (Figure 2-39 on page 2-56).
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| M7A3P400-FGG484I | FPGA, 400000 GATES, 350 MHz, PBGA484 |
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