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| 型號(hào)： | M7A3P400-FG256 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PBGA256 |
| 封裝： | 1 MM PITCH, FBGA-256 |
| 文件頁(yè)數(shù)： | 125/246頁(yè) |
| 文件大小： | 3010K |
| 代理商： | M7A3P400-FG256 |
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SAM G51 [DATASHEET]
11209C–ATARM–20-Dec-13
10.8
Nested Vectored Interrupt Controller (NVIC)
This section describes the NVIC and the registers it uses. The NVIC supports:
Up to 47 interrupts.
A programmable priority level of 0–15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is
the highest interrupt priority.
Level detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no
instruction overhead. This provides low latency exception handling.
10.8.1 Level-sensitive Interrupts
The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral
deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripheral, causing it to clear the
interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and
Software Control of Interrupts” ). For a level-sensitive interrupt, if the signal is not deasserted before the processor
returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means
that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.
10.8.1.1
Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
The NVIC detects a rising edge on the interrupt signal
A software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending Registers” , or
to the NVIC_STIR to make an interrupt pending, see “Software Trigger Interrupt Register” .
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then:
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt
signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive.
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change.
Otherwise, the state of the interrupt changes to inactive.
10.8.2 NVIC Design Hints and Tips
Ensure that the software uses correctly aligned register accesses. The processor does not support unaligned accesses
to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking
that interrupt.
Before programming SCB_VTOR to relocate the vector table, ensure that the vector table entries of the new vector table
are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the “Vector Table
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3P400-FG484I | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| M7A3P400-FG484 | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| M7A3P400-FGG144I | FPGA, 400000 GATES, 350 MHz, PBGA144 |
| M7A3P400-FGG144 | FPGA, 400000 GATES, 350 MHz, PBGA144 |
| M7A3P400-FGG256I | FPGA, 400000 GATES, 350 MHz, PBGA256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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