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參數(shù)資料
| 型號(hào)： | M7A3P1000-2FGG484I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 122/220頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 1M 484-FBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | ProASIC3 |
| RAM 位總計(jì)： | 147456 |
| 輸入/輸出數(shù)： | 300 |
| 門(mén)數(shù)： | 1000000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-FPBGA（23x23） |
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Datasheet Information
5-2
Revision 13
Revision 11
(March 2012)
Note indicating that A3P015 is not recommended for new designs has been added.
The "Devices Not Recommended For New Designs" section is new (SAR 36760).
The following sentence was removed from the "Advanced Architecture" section: "In
addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface" (SAR
34687).
The reference to guidelines for global spines and VersaTile rows, given in the
"Global Clock Contribution—PCLOCK" section, was corrected to the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric
Figure 2-3 Input Buffer Timing Model and Delays (example) has been modified for
the DIN waveform; the Rise and Fall time label has been changed to tDIN (35430).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O
Software Settings" section (SAR 34883).
Added values for minimum pulse width and removed the FRMAX row from
Use the software to determine the FRMAX for the device you are using (SARs
37279, 29269).
Revision 10
(September 2011)
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in the
industry (SAR 32865).
The value of 34 I/Os for the QN48 package in A3P030 was added to the "I/Os Per
Package 1" section (SAR 33907).
The Y security option and Licensed DPA Logo were added to the "ProASIC3
Ordering Information" section. The trademarked Licensed DPA Logo identifies that a
product is covered by a DPA counter-measures license from Cryptography
Research (SAR 32151).
The "Specifying I/O States During Programming" section is new (SAR 21281).
In Table 2-2 Recommended Operating Conditions 1,2, VPUMP programming
voltage in programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45" (SAR
30666). It was corrected in v2.0 of this datasheet in April 2007 but inadvertently
changed back to “3.0 to 3.6 V” in v1.4 in August 2009. The following changes were
VCCPLL analog power supply (PLL) was changed from "1.4 to 1.6" to "1.425 to
1.575" (SAR 33850).
For VCCI and VMV, values for 3.3 V DC and 3.3 V DC Wide Range were corrected.
The correct value for 3.3 V DC is "3.0 to 3.6 V" and the correct value for 3.3 V Wide
Range is "2.7 to 3.6" (SAR 33848).
update to restore values to the correct columns. Previously the Slew Rate column
was missing and data were aligned incorrectly (SAR 34034).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics –
tables were revised for clarification. They now state that the minimum drive strength
for the default software configuration when run in wide range is ±100 A. The drive
strength displayed in software is supported in normal range only. For a detailed I/V
curve, refer to the IBIS models (SAR 25700).
Revision
Changes
Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSC50DRYN-S13 | CONN EDGECARD 100PS .100 EXTEND |
| M7A3P1000-2FG484I | IC FPGA 1KB FLASH 1M 484-FBGA |
| EP4CE55F29C8L | IC CYCLONE IV FPGA 55K 780FBGA |
| HSC50DRYH-S13 | CONN EDGECARD 100PS .100 EXTEND |
| EP4CE55F29C7 | IC CYCLONE IV FPGA 55K 780FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A3P1000-2PQ208 | 功能描述:IC FPGA 1KB FLASH 1M 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| M7A3P1000-2PQ208I | 功能描述:IC FPGA 1KB FLASH 1M 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| M7A3P1000-2PQG208 | 功能描述:IC FPGA 1KB FLASH 1M 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| M7A3P1000-2PQG208I | 功能描述:IC FPGA 1KB FLASH 1M 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| M7A3P1000-FG144 | 功能描述:IC FPGA 1KB FLASH 1M 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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