參數(shù)資料
型號(hào): M74VHC1GT126DF1G
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/6頁(yè)
文件大?。?/td> 0K
描述: IC BUFF CMOS LVL/SFTR N-I SOT353
產(chǎn)品變化通告: Wire Change for SC88/A 17/Jun/2011
標(biāo)準(zhǔn)包裝: 1
系列: 74VHC
邏輯類(lèi)型: 緩沖器/線路驅(qū)動(dòng)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 1
輸出電流高,低: 8mA,8mA
電源電壓: 3 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 6-TSSOP(5 引線),SC-88A,SOT-353
供應(yīng)商設(shè)備封裝: SC-70
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: M74VHC1GT126DF1GOSDKR
Semiconductor Components Industries, LLC, 2012
May, 2012 Rev. 15
1
Publication Order Number:
MC74VHC1GT126/D
MC74VHC1GT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTLCompatible Inputs
The MC74VHC1GT126 is a single gate noninverting 3state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC1GT126 requires the 3state control input (OE) to be
set Low to place the output into the high impedance state.
The device input is compatible with TTLtype input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logiclevel translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the highvoltage power supply.
The MC74VHC1GT126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT126 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOSCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 62; Equivalent Gates = 16
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree and are RoHS Compliant
Figure 1. Pinout (Top View)
IN A
OUT Y
VCC
OE
IN A
OUT Y
GND
OE
Figure 2. Logic Symbol
1
2
3
4
5
PIN ASSIGNMENT
1
2
3
GND
OE
IN A
4
5VCC
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
H
X
A Input
Y Output
L
H
Z
OE Input
H
L
http://onsemi.com
SC88A / SOT353 / SC70
DF SUFFIX
CASE 419A
TSOP5 / SOT23 / SC59
DT SUFFIX
CASE 483
MARKING
DIAGRAMS
1
5
1
5
1
5
W3 M G
G
W3
= Device Code
M
= Date Code*
G
= PbFree Package
1
5
W3 M G
G
M
*Date Code orientation and/or position may vary
depending upon manufacturing location.
(Note: Microdot may be in either location)
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