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參數(shù)資料
| 型號： | M74HCT393M1R |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL BINARY COUNTER |
| 中文描述： | 雙二進制計數(shù)器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 254K |
| 代理商： | M74HCT393M1R |
M54HCT393
M74HCT393
October 1993
DUAL BINARY COUNTER
B1R
(Plastic Package)
ORDER CODES :
M54HCT393F1R
M74HCT393B1R
M74HCT393M1R
M74HCT393C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
DESCRIPTION
.
HIGH SPEED
f
MAX
= 80 MHz (TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS393
The M54/74HCT393 is a high speed CMOS DUAL
BINARY COUNTER fabricated in silicon gate
C
2
MOS technology. It has the same high speed
performance of LSTTL combined with true COMS
low powerconsumption.
This counter circuit contains independent ripple
carry counters and two 4-bit ripple carry binary
counters, which can be cascated to create a single
divideby 256 counter.
Each 4-bit counter isincremented on thehightolow
transition (negative edge) of the clock input,and
each has an independent clear input. When clear is
set to high all four bits of each counter are set to a
low level. This enables counttruncation and allows
the
implementation
of
configurations.
This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M54/74HCT devices are
designed to directly interface HSC
2
MOS systems
with TTL and NMOS components. They are also
plug in replacements for LSTTL devices giving a
reduction of power consumption.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
divide
by
N counter
1/12
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