參數(shù)資料
型號: M74HCT137C1R
廠商: 意法半導(dǎo)體
英文描述: 3 TO 8 LINE DECODER/LATCH INVERTING
中文描述: 3至8線譯碼器/鎖存器反相
文件頁數(shù): 1/12頁
文件大小: 260K
代理商: M74HCT137C1R
M54HCT137
M74HCT137
February 1993
3 TO 8 LINE DECODER/LATCH (INVERTING)
B1R
(Plastic Package)
ORDER CODES :
M54HCT137F1R
M74HCT137M1R
M74HCT137B1R
M74HCT137C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
DESCRIPTION
.
HIGH SPEED
tPD = 17 ns (TYP.) AT VCC =5 V
.
LOW POWER DISSIPATION
ICC =4
A (MAX.) AT TA =25 °C
.
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH =IOL = 4 mA (MIN.)
.
BALANCED PROPAGATION DELAYS
tPLH =tPHL
.
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS137
The M54/74HCT137 is a high speed CMOS3TO8LINE
DECODER/LATCH (INVERTING) fabricated in silicon
gateC
2MOStechnology. Ithas the samehigh speed per-
formance ofLSTTL combined with trueCMOSlow power
consumption. This device is a 3 to 8 line decoder with lat-
ches onthe three address inputs. When GLgoes from low
to high, the address present at the select inputs (A, B and
C) is stored in the latches. As long as GLremains high no
address changes will be recognized. Output enable pins
G1 and G2, control the state of the outputs independently
ofthe select or latch-enable inputs. All theoutputs are high
unless G1 is high and G2 is low. The HC137 is ideally
suited for the implementation of glitch-free decoders in
stored-address applications in bus oriented systems. All
inputs are equipped with protection circuits against static
discharge and transient excess voltage.This integrated
circuit has input and output characteristics that are fully
compatible with 54/74 LSTTL logic families. M54/74HCT
devices aredesigned todirectly interfaceHSC
2MOS sys-
tems with TTL and NMOS components. They are also
plug in replacements for LSTTL devices giving a re-
duction of power consumption.
1/12
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