參數(shù)資料
型號(hào): M74HC690TTR
廠商: STMICROELECTRONICS
元件分類: 計(jì)數(shù)器
英文描述: HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO20
封裝: TSSOP-20
文件頁數(shù): 16/17頁
文件大?。?/td> 839K
代理商: M74HC690TTR
M74HC690
8/17
CAPACITIVE CHARACTERISTICS
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
fMAX
Maximum Clock
Frequency
2.0
50
4.4
12
3.6
3
MHz
4.5
22
45
18
15
6.0
26
53
21
18
tPZL tPZH High Impedance
Output Enable
Time
2.0
50
RL = 1 K
48
120
150
180
ns
4.5
15
24
30
36
6.0
13
20
26
31
2.0
150
RL = 1 K
61
150
190
225
ns
4.5
19
30
38
45
6.0
17
26
32
38
tPLZ tPHZ High Impedance
Output Disable
Time
2.0
50
RL = 1 K
32
145
180
220
ns
4.5
15
29
36
44
6.0
13
25
31
37
tW(L)
tW(H)
Minimum Pulse
Width (CCK, RCK)
2.0
50
28
75
95
110
ns
4.5
7
151922
6.0
6
131619
tW(L)
Minimum Pulse
Width (CCLR -
RCLR)
2.0
50
40
75
95
110
ns
4.5
8
151922
6.0
7
131619
ts
Minimum Set-up
Time (LOAD, ENT,
ENP)
2.0
50
68
150
190
220
ns
4.5
17
30
38
44
6.0
14
26
32
37
ts
Minimum Set-up
Time (A, B, C, D)
2.0
50
44
100
125
145
ns
4.5
11
20
25
29
6.0
9
172125
ts
Minimum Set-up
Time (CCK - RCK)
2.0
50
48
125
155
180
ns
4.5
12
25
31
36
6.0
10
21
26
31
th
Minimum Hold
Time
2.0
50
000
ns
4.5
0
6.0
0
tREM
Minimum Removal
Time
2.0
50
25
30
40
ns
4.5
5
6
8
6.0
5
7
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
CIN
Input Capacitance
5
101010
pF
CPD
Power Dissipation
Capacitance (note
1)
70
pF
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
CL
(pF)
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
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