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參數(shù)資料
| 型號： | M74HC651M1R |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | HC652 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HC651 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV. |
| 中文描述： | HC652八路總線收發(fā)器/注冊3態(tài)HC651八路總線收發(fā)器/注冊三態(tài)，刑事調(diào)查。 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 202K |
| 代理商： | M74HC651M1R |
M74HC651
M74HC652
October 1993
HC652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
.
HIGH SPEED
f
MAX
= 73 MHz (TYP.) AT V
CC
= 5V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28% V
CC (
MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 6 mA (mIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR)= 2 VTO 6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS651/652
HC651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
B1R
(Plastic Package)
ORDER CODES :
M74HCXXXM1R
M74HCXXXB1R
M1R
(MicroPackage)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS
(top view)
DESCRIPTION
M74HC651/652 are high speed CMOS OCTAL
BUS TRANSCEIVERS AND REGISTERS (3-
STATE), fabricated in silicon gate C
2
MOS technol-
ogy. They have the same high speedperformance
of LSTTLcombined with trueCMOSlow powercon-
sumption. These devices consist of bus transceiver
circuits, D-type flip-flops, and control circuitry ar-
rangedfor multiplexed transmission of data directly
from the input bus or fromthe internal storage reg-
isters.EnableGABand GBAare provided tocontrol
the transceiver functions.
Select AB and Select BA controlpins are provided
to select whether real-time or stored data is trans-
fered. A low input level selects real-time data, and
a highselects stored data.
Data on the Aor Bbus, or both, can bestoredin the
internal D flip-flops by low-to-high transitions at the
appropriate clock pins (CLOCK AB or CLOCK BA)
regardlessoftheselectorenablecontrolpins.When
selectAB andselectBA are inthereal-time transfer
mode, it is also possible tostore data without using
the internal D-type flip-flops by simultaneously en-
ablingGABandGBA.Inthisconfiguration eachout-
put reinforces its input. Thus, when all other data
sources to the two sets of bus lines are at high im-
pedance, each set of bus lines will remain at its last
state.Allinputs areequipped withprotectioncircuits
against static discharge and transient excess volt-
age.
GAB, GAB, CAB,
SAB,SBA, CBA
A, B
1/12
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