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參數(shù)資料
| 型號： | M74HC620RM13TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | HC/UH SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 312K |
| 代理商： | M74HC620RM13TR |
1/11
August 2001
s
HIGH SPEED:
tPD = 10 ns (TYP.) at VCC = 6V
s
LOW POWER DISSIPATION:
ICC = 4A(MAX.) at TA=25°C
s
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 6mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 620
DESCRIPTION
The 74HC620 is an advanced high-speed CMOS
OCTAL
BUS
TRANSCEIVER
(3-STATE)
fabricated with silicon gate C2MOS technology.
This IC is intended for two-way asynchronous
communication between data buses. The control
function
implementation
allows
maximum
flexibility in timing.
This device allows data transmission from the A
bus to B bus or from the B to the A bus depending
upon the logic level levels at the enable inputs
(GBA and GAB). The enable inputs can be used to
disable the device so that the buses are effectively
isolated. The dual enable configuration gives this
device
the
capability
to
store
data
by
simultaneous enabling of GBA and GAB.
Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets
of bus lines are at high impedance, both sets of
bus lines (16 in all) will remain at their last states.
The 8-bit codes appearing on the two sets of
buses will be complementary.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC620
OCTAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS (INVERTING)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HC620B1R
SOP
M74HC620M1R
M74HC620RM13TR
TSSOP
M74HC620TTR
TSSOP
DIP
SOP
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