參數(shù)資料
型號: M74HC564
廠商: 意法半導體
英文描述: Octal D-Type Latch with 3 State Output(八D觸發(fā)器帶三態(tài)輸出(同相))
中文描述: 八路D類3態(tài)輸出鎖存(八?觸發(fā)器帶三態(tài)輸出(同相))
文件頁數(shù): 1/13頁
文件大?。?/td> 271K
代理商: M74HC564
M54/74HC564
M54/74HC574
March 1993
HC564 INVERTING - HC574 NON INVERTING
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28% V
CC
(MIN)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OL
=
I
OH
= 6 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS564/574
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTION
(top view)
.
HIGH SPEED
f
MAX
= 62 MHz (TYP.) AT V
CC
= 5 V
DESCRIPTION
The M54/74HC564 and M54HC574 are high speed
CMOSOCTAL D-TYPEFLIPFLOPWITH3-STATE
OUTPUTS fabricated with in silicon gate C
2
MOS
technology. They have the same high speed per-
formance of LSTTL combined with true CMOS low
power comsuption. These8-bit D-type flip-flops are
controlled by aclockinput(CK) and anouputenable
input(OE).On thepositivetransition oftheclock,the
Qoutputswillbesettothelogicstatethatweresetup
at the D inputs (HC574) or their complements
(HC564).
While the OE input is low, the eight outputs will be
in a normal logic state (high or low logic level), and
while high level, the outputs will be in a high imped-
ance state.The outputcontrol does notaffect thein-
ternaloperation offlip-flops.That is,theolddatacan
be retained or the new data can be entered even
while the outputs are off. The application engineer
has a choice of combination of inverting andnon-in-
verting outputs. The 3-state output configuration
and thewide choice of outline make bus-organized
systemssimple.Allinputs are equipped withprotec-
tion circuits against static discharge and transient
excess voltage.
1/13
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相關代理商/技術參數(shù)
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