參數(shù)資料
型號(hào)： M74HC4514TTR
廠商： 意法半導(dǎo)體
英文描述： 4 TO 16 LINE DECODER/LATCH
中文描述： 4至16線譯碼器/鎖存
文件頁數(shù)： 1/12頁
文件大?。?/td> 289K
代理商： M74HC4514TTR
1/12
April 2003
I
HIGH SPEED:
t
PD
= 20 ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4514
I
I
I
I
I
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DESCRIPTION
The M74HC4514 is an high speed CMOS 4 LINE
TO 16 LINE SEGMENT DECODER WITH
LATCHED INPUTS fabricated with silicon gate
C
2
MOS technology.
A binary code stored in the four input latches (A to
D) provides a high level at the selected one of
sixteen outputs excluding the other fifteen outputs,
when the inhibit input (INHIBIT) is held low. When
the inhibit input (INHIBIT) is held high, all outputs
are kept low level, while the latch function is
available. The data applied to the data inputs are
transferred to the Q outputs of latches when the
strobe input is held high. When the strobe input is
taken low, the information data applied to the data
input at a time is retained at the output of the
latches.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC4514
4 TO 16 LINE DECODER/LATCH
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
SOP
TSSOP
M74HC4514B1R
M74HC4514M1R
M74HC4514RM13TR
M74HC4514TTR
TSSOP
DIP
SOP
相關(guān)PDF資料
PDF描述
M74HC4518M1R TERM. F/O CABLE SC-SC/ DPLX/RISER/1M/ORANGE
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M74HC4518B1R HC4518 DUAL DECADE COUNTER HC4520 DUAL 4 BIT BINARY COUNTER
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M74HC4518F1R HC4518 DUAL DECADE COUNTER HC4520 DUAL 4 BIT BINARY COUNTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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M74HC4515M1R 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH INV.
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