參數(shù)資料
型號: M74HC4022B1R
廠商: 意法半導體
英文描述: 8-Bit, 1 us Dual DAC, Serial Input, Pgrmable Int. Ref., Settling Time 8-SOIC 0 to 70
中文描述: 八進制計數(shù)器/除法器
文件頁數(shù): 1/12頁
文件大?。?/td> 256K
代理商: M74HC4022B1R
M54HC4022
M74HC4022
October 1992
OCTAL COUNTER/DIVIDER
B1R
(Plastic Package)
ORDER CODES :
M54HC4022F1R
M74HC4022B1R
M74HC4022M1R
M74HC4022C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
DESCRIPTION
.
HIGH SPEED
f
MAX
= 57 MHz (TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
4
μ
A(MAX.) at T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 4022B
The M54/74HC4022 isa high speedCMOSOCTAL
COUNTER/DIVIDER fabricated in silicon gate
C
2
MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
It contains a 4-stage divide-by-8 Johnson counter
with 8decoded outputs (Q0-Q7) and a Carry-out bit.
Thiscounter isadvanced on the positive edge ofthe
clock signal when CLOCK ENABLE input is held
low, or is advanced on the negative edge of clock
enable signalwhen CLOCKinput is held high, and
the selectedone of eight outputsgoes high.Holding
the CLEAR input high clears the counter to zerore-
gardless of the other input conditions. All inputs are
equipped with protection circuits against static dis-
charge and transient excess voltage.
1/12
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