參數(shù)資料
型號: M74HC375
廠商: 意法半導(dǎo)體
英文描述: Quad D-Type Latch(四D鎖存器)
中文描述: 四D型鎖存器(四?鎖存器)
文件頁數(shù): 1/11頁
文件大?。?/td> 244K
代理商: M74HC375
M54HC375
M74HC375
February 1993
QUAD D TYPE LATCH
B1R
(Plastic Package)
ORDER CODES :
M54HC375F1R
M74HC375B1R
M74HC375M1R
M74HC375C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
DESCRIPTION
The M54/74HC375 isahighspeed CMOS QUADD
TYPE LATCH fabricated in silicon gate C
2
MOS
technology. It has the same high speed perform-
anceofLSTTL combinedwithtrue CMOSlowpower
consumption. It contains twogroups of 2-bit latches
controlled by an enable input (G1
.
2 or G3
.
4).
These two latchgroups can be used inthedifferent
circuits. Each latch hasQ and Q outputs (1Q to 4Q
and 1Q to 4Q). The data applied to the data input is
transferred to the Q and Qoutputs when the enable
input is taken high and the outputs will follow the
data input as long as the enable input is kepthigh.
When the enable input is taken low,the information
data applied tothedata input at that timeisretained
at the outputs.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
.
HIGH SPEED
t
PD
= 14 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 1
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS375
1/11
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