參數(shù)資料
型號(hào)： M74HC280M1R
廠(chǎng)商： 意法半導(dǎo)體
英文描述： 10-Bit, 2.5 us Dual DAC, Serial Input, Pgrmable Settling Time 8-SOIC -40 to 85
中文描述： 9位奇偶發(fā)生器
文件頁(yè)數(shù)： 1/10頁(yè)
文件大?。?/td> 242K
代理商： M74HC280M1R
M54HC280
M74HC280
October 1992
9 BIT PARITY GENERATOR
B1R
(Plastic Package)
ORDER CODES :
M54HC280F1R
M74HC280B1R
M74HC280M1R
M74HC280C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
.
HIGH SPEED
t
PD
= 22 ns(TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) at T
A
= 25
°
C6 V
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS280
The M54/74HC280 is a high speed CMOS 9-BIT
PARITY GENERATOR fabricated in silicon gate
C
2
MOStechnology.Ithas thesame highspeedper-
formance of LSTTL combined with true CMOS low
consumption.
It is composed of nine data inputs (A to I) and
odd/even parity outputs (
Σ
ODD and
Σ
EVEN). The
ninedatainputscontrol theoutput conditions.When
the number of highlevel inputs isodd,
Σ
ODDoutput
is kept high and
Σ
EVEN output low. Conversely,
when the number is even ,
Σ
EVEN output is kept
high and
Σ
ODD low.
This IC generates either odd or even parity making
it flexible application.
The word-length capability is easily expanded by
cascading.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
DESCRIPTION
1/10
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