參數(shù)資料
型號(hào)： M74HC259TTR
廠商： STMICROELECTRONICS
元件分類： 鎖存器
英文描述： HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16
封裝： TSSOP-16
文件頁(yè)數(shù)： 1/13頁(yè)
文件大?。?/td> 555K
代理商： M74HC259TTR
1/13
July 2001
s
HIGH SPEED :
tPD = 20 ns (TYP.) at VCC = 6V
s
LOW POWER DISSIPATION:
ICC =4A(MAX.) at TA=25°C
s
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 259
DESCRIPTION
The M74HC259 is an high speed CMOS 8 BIT
ADDRESSABLE LATCH fabricated with silicon
gate C2MOS technology.
The M74HC259 has single data input (D) 8 latch
outputs (Q0-Q7), 3 address inputs (A, B, and C),
common enable input (E), and a common CLEAR
input. To operate this device as an addressable
latch, data is held on the D input, and the address
of the latch into which the data is to be entered is
held on the A, B, and C inputs. When ENABLE is
taken low the data flows through to the addresses
output. The data is stored on the positive-going
edge of the ENABLE pulse. All unaddressed
latches will remain unaffected. With ENABLE in
the high state the device is deselected and all
latches remain in their previous state, unaffected
by changes on the data or address inputs. To
eliminate the possibility of entering erroneous data
into the latches, the ENABLE should be held high
(inactive) while the address lines are changing. If
ENABLE is held high and CLEAR is taken low all
eight latches are cleared to the low state. If
ENABLE is low all latches except the addressed
latch will be cleared. The addressed latch will
instead
follow
the
D
input,
effectively
implementing a 3-to-8 line decoder.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC259
8 BIT ADDRESSABLE LATCH
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HC259B1R
SOP
M74HC259M1R
M74HC259RM13TR
TSSOP
M74HC259TTR
TSSOP
DIP
SOP
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