參數(shù)資料
型號: M74HC237TTR
廠商: 意法半導(dǎo)體
英文描述: 2A Standard Fixed Output LDO Regulators; Package: TO220FP-3; Constitution materials list: Packing style: Tube packaging; Package quantity: 50; Minimum package quantity: 500;
中文描述: 3至8線譯碼器鎖存
文件頁數(shù): 1/11頁
文件大?。?/td> 192K
代理商: M74HC237TTR
1/11
July 2001
I
HIGH SPEED:
t
PD
= 16ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 237
I
I
I
I
I
I
DESCRIPTION
The M74HC237 is an high speed CMOS 3 TO 8
LINE DECODER fabricated with silicon gate
C
2
MOS technology.
When GL goes from low to high, the address
present at the select inputs (A, B, C) is stored in
the latches. As long as GL remains high no
address changes will be recognized. Output
enable controls, G1 and G2 control the state of the
outputs
independently
of
the
select
or
latch-enable inputs. All of the outputs are low
unless G1 is high and G2 is low. The M74HC237
is ideally suited for the implementation of
glitch-free
decoders
applications in bus oriented systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
in
stored-address
M74HC237
3 TO 8 LINE DECODER LATCH
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
SOP
TSSOP
M74HC237B1R
M74HC237M1R
M74HC237RM13TR
M74HC237TTR
TSSOP
DIP
SOP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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