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參數(shù)資料
| 型號(hào)： | M7040N-100ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| 中文描述： | 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎 |
| 文件頁(yè)數(shù)： | 38/159頁(yè) |
| 文件大?。?/td> | 1088K |
| 代理商： | M7040N-100ZA1T |
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M7040N
38/159
Table 24. WRITE Address Format for Internal Registers
Table 25. WRITE Address Format for Data and Mask Array (Burst Write)
Parallel WRITE
In order to write the data and mask arrays faster
for initialization, testing, or diagnostics, many loca-
tions can be written simultaneously in the M7040N
device. When CMD[9] is set in Cycles A and B of
the WRITE command during a WRITE to the data
or mask arrays, the address present on DQ[10:1]
that specifies 64 locations in a device is used and
64 72-bit locations are simultaneously written in ei-
ther the data or mask array.
SEARCH COMMAND
The M7040N (Silicon) Search Engine can be con-
figured in four ways:
1. 72-bit
2. 144-bit (page )
3. 288-bit (page )
4. Mixed-sizes on tables configured with differ-
ent widths using an M7040N with CFG_L low
or CFG_L high (page )
72-bit Configuration with Single Device
The hardware diagram of the search subsystem of
a single device is shown in Figure 22. Figure 23,
page 40 shows the timing diagram for a SEARCH
operation in the 72-bit configuration (CFG =
0000000000000000) for one set of parameters.
This illustration assumes that the host ASIC has
programmed TLSZ to '00,' HLAT to '000,' LRAM to
'1,' and LDEV to '1' in the command register.
The following is the sequence of operations for a
single 72-bit SEARCH command.
–
Cycle A:
The host ASIC drives CMDV high and
applies the SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10], CMD[5:3] must be
driven with the index to the global mask register
pair for use in the SEARCH operation. CMD[8:6]
signals must be driven with the same bits that
will be driven on SADR[23:21] by this device if it
has a hit. DQ[71:0] must be driven with the 72-
bit data to be compared. The CMD[2] signal
must be driven to Logic '0.'
–
Cycle B:
The host ASIC continues to drive
CMDV high and applies the SEARCH command
('10') on CMD[1:0]. CMD[5:2] must be driven by
the index of the comparand register pair for stor-
ing the 144-bit word presented on the DQ Bus
during Cycles A and B. CMD[8:6] signals must
be driven with the index of the SSR that will be
used for storing the address of the matching en-
try and the Hit Flag (see SEARCH-Successful
Registers (SSR[0:7]), page 24). The DQ[71:0]
continues to carry the 72-bit data to be com-
pared.
Note:
In the 72-bit configuration, the host ASIC
must supply the same data on DQ[71:0] during
both Cycles A and B. The even and odd pair of
GMRs selected for the comparison must be pro-
grammed with the same value.
DQ[71:26]
DQ[25:21]
DQ[20:19]
DQ[18:7]
DQ[6:0]
Reserved
ID
11: Register
Reserved
Register address
DQ
[71:26]
DQ
[25:21]
DQ
[20:19]
DQ
[18:16]
DQ
[15:0]
Reserved
ID
00: Data array
Reserved
Don
’
t care. These 16 bits come from the internal
register (WBURADR), which increments with each
access.
Reserved
ID
01: Mask
array
Reserved
Don
’
t care. These 16 bits come from the internal
register (WBURADR), which increments with each
access.
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